Method and apparatus for generating design information, and...

Details Method and apparatus for generating design information, and... Method and apparatus for generating design information, and...

2005-10-18

2008-10-21

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07441221

ABSTRACT:
An apparatus generates design information on a via hole that passes through predetermined layers of a multilayer wiring board, by storing information on at least one of a shape and a size of a land to be provided around the via hole. When designing a via hole that passes through a plurality of internal layers of the wiring board, the land information for an internal layer is applied to each internal layer through which the via hole passes.

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patent: 6886151 (2005-04-01), Tanaka
patent: 2002/0174413 (2002-11-01), Tanaka
patent: 2004/0104042 (2004-06-01), Takase et al.
patent: 2004/0176938 (2004-09-01), Gisin et al.
patent: 2005/0077083 (2005-04-01), Mattix
patent: 3-231371 (1991-10-01), None
patent: 2002-342398 (2002-11-01), None
Kinji Ito, “Prinited Wiring Technical Reader”, p. 193, 2NDEdition, Published by the Nikkan Kogyo Shimbun Co., Ltd, May 1989.

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