Method and apparatus for generating bit errors in a forward...

Details Method and apparatus for generating bit errors in a forward... Method and apparatus for generating bit errors in a forward...

2006-07-04

2006-07-04

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07073117

ABSTRACT:
A method and apparatus for generating and inserting bit errors in data words that have been encoded in a forward error correction (FEC) system in order to estimate power dissipation. In accordance with the present invention, it has been determined that a burst error generator that is capable of erroring the maximum number of correctable data bits in every FEC encoded frame, which allows the designer to accurately produce test vectors that are suitable for use in commercially available power estimation tools. In addition, after the IC is produced, the burst error generator of the present invention can be enabled to provide real-time FEC power dissipation data for use in system thermal modeling, thus obviating the need to use costly external devices that emulate a given error rate. Furthermore, the power dissipation data obtained in real-time may be used to refine the initial design power estimate, which will then allow the designer to develop a more accurate prediction of power consumption for future IC designs. Thus, the burst error generator of the present invention is capable of reducing iterations of IC designs by accurately estimating the worst-case power dissipation of FEC decoders.

REFERENCES:
patent: 4488302 (1984-12-01), Ahamed
patent: 6357030 (2002-03-01), Demura et al.
patent: 6799287 (2004-09-01), Sharma et al.
ITU ANSI T1.105.08-2001, Synchronous Optical Network (SONET)- In-band Forward Error Correction Code Specifications□□.
ALTERA White Paper titled “Enhancing High-Speed Telecommunications Networks with FEC” Feb. 2001 ver. 1.0.
IEEE 802.3ah EFM Task Force Interim Meeting, Los Angeles Oct. 2001.

Affiliated with

Also associated with

Rating

Method and apparatus for generating bit errors in a forward... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for generating bit errors in a forward..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for generating bit errors in a forward... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3592280