Method and apparatus for generating and verifying libraries...

Details Method and apparatus for generating and verifying libraries... Method and apparatus for generating and verifying libraries...

2006-06-20

2006-06-20

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07065724

ABSTRACT:
A method generates and verifies a design-for-test (DFT) library for an automatic test pattern generator (ATPG) tool. The method includes (a) creating a synthesis library including primitives to be used to create the modules, the primitives being the same as primitives used by the ATPG tool, (b) creating a register transfer level (RTL) description for each module, (c) performing synthesis using the synthesis library and the RTL description to create a gate level description for each module, and (d) generating the DFT library by converting a hardware description language (HDL) of the gate level description into a script language for the ATPG tool to create a DFT file for each module. The method may further include (e) converting the DFT files into a RTL description to create a pseudo-RTL description for each module, and (f) comparing the RTL description and the pseudo-RTL description for verification of the DFT library.

REFERENCES:
patent: 6195776 (2001-02-01), Ruiz et al.
patent: 6301688 (2001-10-01), Roy
patent: 6463560 (2002-10-01), Bhawmik et al.
patent: 6665844 (2003-12-01), Stanion
patent: 6925617 (2005-08-01), Bayraktaroglu et al.

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