Method and apparatus for generating an error detection code for

Details Method and apparatus for generating an error detection code for Method and apparatus for generating an error detection code for

1997-06-03

1999-08-10

Moise, Emmanuel L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714807, H03M 1300, G06F 1110

Patent

active

059352680

ABSTRACT:
A method and apparatus for generating an error detection code, such as a Cyclic Redundancy Checksum (CRC), for a modified binary data block. The modified data block, such as a VLAN frame, is derived from an original binary data block, such as an ethernet frame, having a first error detection code associated therewith. In one embodiment, the method requires modifying the original data block utilizing first data, in the form of VLAN header information, to generate the VLAN frame, whereafter a second error detection code is calculated exclusively for the VLAN header information. More specifically, where the original data block is modified by the insertion of the VLAN header information into the original data block, a CRC is calculated using the VLAN header information shifted to a position corresponding to its position within the modified data block. Having calculated the second error detection code, the first and second error detection codes are added so as to generate a third error detection code, which is associated with the VLAN frame. The first and second error detection codes are binary values, and the step of adding comprises XORing the first and second error detection codes. The third error detection code is also a binary value and has a bit-length equal to that of the first error detection code.

REFERENCES:
patent: 5062111 (1991-10-01), Gotou et al.
patent: 5694407 (1997-12-01), Glaise
patent: 5742604 (1998-04-01), Edsall et al.
patent: 5859837 (1999-01-01), Crayford

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