Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent
1995-10-30
1997-06-10
Hudspeth, David R.
Electronic digital logic circuitry
Multifunctional or programmable
Array
326 40, 326 46, 326 93, H03K 19177
Patent
active
056380089
ABSTRACT:
A method and apparatus for generating an asynchronously clocked signal in a synchronously clocked programmable device is described. A programmable logic device having synchronously clocked or product term clocked registers receives an input signal and an event signal. The input signal and the event signal can be any externally or internally generated signals. The event signal signifies the occurrence of a particular event by transitioning from one signal state to another. The input signal is asynchronously clocked through the synchronously clocked PLD without utilizing the synchronously clocked or product term clocked registers. The input signal is asynchronously clocked in response to an edge transition of the event signal. The edge transition of the event signal being either a failing edge or a rising edge.
REFERENCES:
patent: 4912342 (1990-03-01), Wong et al.
patent: 5231312 (1993-07-01), Gongwer et al.
patent: 5254886 (1993-10-01), El-Ayat et al.
patent: 5258668 (1993-11-01), Cliff et al.
patent: 5450608 (1995-09-01), Steele
Cypress Semiconductor Corporation Programmable Logic Data Book, "CY7C340 EPLD Family: Multiple Array Matrix High-Density EPLD's"; pp. 3-1 to 3-5; Jul., 1994.
Cypress Semiconductor Corporation Programmable Logic Data Book, "CY7C341 CYC341B: 192-Macrocell MAX .RTM. EPLD's"; pp. 3-7 to 3-9; Jul., 1994.
Cypress Semiconductor Corporation Programmable Logic Data Book, "pASIC380 Family: Very High Speed CMOS FPGA's"; pp. 4-1 to 4-7; Jul., 1994.
FLASH370.TM. Preliminary CPLD Family: High-Density Flash CPLDs, Cypress Semiconductor Corp Databook, 1992, pp. 3-92 to 3-98.
Larcher Philippe
Rangasayee Krishna
Cypress Semiconductor Corp.
Hudspeth David R.
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