Method and apparatus for generating addresses in parallel proces

Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address

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711214, 711215, 711217, 711218, 711219, G06F 1206

Patent

active

058359710

ABSTRACT:
An apparatus for generating an address to increase efficiency in parallel processing in a multiprocessor system. A global address generating unit is provided within a vector unit of each of processing elements (PE) constituting a parallel computer system. An adder provided within the global address generating unit sequentially adds an increment of an address, d.sub.-- Adr.sub.-- exl, and d.sub.-- Adr.sub.-- in to an address Adr.sub.-- exl and Adr.sub.-- in, respectively. A subtracter outputs a quotient obtained by dividing d.sub.-- Adr.sub.-- exl by band width bexl as a logical PE number. Additionally, a remainder obtained as an output from a subtracter is added to Adr.sub.-- in, thereby enabling a logical in-PE address to be obtained. The logical PE number and the logical in-PE address thus obtained are converted to a real PE number and a real in-PE address. Generating a global address by hardware reduces overhead incurred by parallel operation of array data.

REFERENCES:
patent: 4939642 (1990-07-01), Blank
patent: 5388220 (1995-02-01), Okabayashi
patent: 5408613 (1995-04-01), Okabayashi
patent: 5418970 (1995-05-01), Gifford

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