Electrical computers and digital processing systems: memory – Address formation – Address multiplexing or address bus manipulation
Patent
1996-03-22
1999-09-21
Coles, Edward L.
Electrical computers and digital processing systems: memory
Address formation
Address multiplexing or address bus manipulation
711217, 711218, 360 49, G06F 926
Patent
active
059567570
ABSTRACT:
A method and apparatus for generating addresses. The present invention provides for fast generation of a series of addresses in an array where the series comprises a column or diagonal of the array, such as for layered ECC code words in CD-ROM. Whereas each address is computable individually using multipliers and modulo circuits, the present invention operates on the series of addresses as a whole, forming a dependence between successive addresses. The dependence is separated into multiple address indices that may be summed together for the desired address. The present invention is thus able to generate a series of addresses by accumulation processes requiring only selection of the appropriate increment value and addition to a previously stored address index value. Address generation throughput is increased with savings in layout area and power.
REFERENCES:
patent: 4901318 (1990-02-01), Tomisawa
patent: 5408477 (1995-04-01), Okada et al.
patent: 5412667 (1995-05-01), Havemose
patent: 5465261 (1995-11-01), Descheme
patent: 5517631 (1996-05-01), Machado et al.
patent: 5627844 (1997-05-01), Cho
patent: 5640286 (1997-06-01), Acosta et al.
Adaptec, Inc.
Coles Edward L.
Nguyen Madeleine A-V
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