Method and apparatus for generating a signal with a voltage inse

Details Method and apparatus for generating a signal with a voltage inse Method and apparatus for generating a signal with a voltage inse

1999-08-11

2000-10-31

Nelms, David

Static information storage and retrieval

Read/write circuit

Signals

36518908, 36518909, G11C 700

Patent

active

06141266&

ABSTRACT:
A delay circuit that generates an output signal responsive to an input signal after a delay corresponding to a reference voltage that is insensitive to the power supply voltage. The output signal switches between ground and the power supply voltage (V.sub.CC). The delay circuit is formed by a timer circuit and a level translator circuit. The delay circuit provides an output signal having a delay of a fixed time period regardless of fluctuations or changes in the supply voltage. The level translator circuit provides an output signal with the aforementioned delay that has a magnitude of either the power supply voltage or ground. The timer circuit includes a capacitor that is charged and discharged through respective transistors to provide the delay. The level translator circuit includes transistors that switch the output signal between the supply voltage and ground.

REFERENCES:
patent: 4660180 (1987-04-01), Tanimura et al.
patent: 5321659 (1994-06-01), Taguchi
patent: 5596545 (1997-01-01), Iin

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