Method and apparatus for generating a reset signal within an int

Details Method and apparatus for generating a reset signal within an int Method and apparatus for generating a reset signal within an int

1997-09-29

1999-10-26

Butler, Dennis M.

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

713600, G06F 104

Patent

active

059745614

ABSTRACT:
An integrated circuit having a terminal for receiving a first signal, a terminal for receiving a second signal, and circuitry for generating a reset signal is disclosed. The reset signal is asserted based on a transition of the first signal when the second signal is in a predetermined state. In one embodiment the first signal is a suspend clock signal, the second signal is a suspend status signal, and the reset signal is used to reset a resume well within the integrated circuit. Thus, the integrated circuit can be used in a computer system which has a suspend mode with a resume sequence during which the resume well is reset, without requiring that the integrated circuit include an extra terminal for indicating when to reset the resume well.

REFERENCES:
patent: 5842028 (1998-11-01), Vajapey
patent: 5903766 (1999-05-01), Walker et al.

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