Method and apparatus for generating a layout for a transistor

Details Method and apparatus for generating a layout for a transistor Method and apparatus for generating a layout for a transistor

2011-04-12

2011-04-12

Rossoshek, Helen (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Optimization

C716S051000, C716S053000, C716S055000, C716S109000, C716S110000, C716S112000, C716S120000, C716S136000, C716S139000

Reexamination Certificate

active

07926018

ABSTRACT:
A system that generates a layout for a transistor is presented. During operation, the system receives a transistor library which includes operating characteristics of fabricated transistors correlated to transistor gate shapes. The system also receives one or more desired operating characteristics for the transistor. Next, the system determines a transistor gate shape for the transistor based on the transistor library so that a fabricated transistor with the transistor gate shape substantially achieves the one or more desired operating characteristics. The system then generates the layout for the transistor which includes the transistor gate shape.

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