Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2003-05-28
2004-11-02
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S534000
Reexamination Certificate
active
06812774
ABSTRACT:
BACKGROUND OF THE INVENTION
This U.S. nonprovisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application 2002-46929, filed on Aug. 8, 2002, the entire contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a method and apparatus for generating a high voltage capable of improving a charge transfer efficiency of a charge transfer transistor.
2. Description of Related Art
A conventional high voltage generating circuit includes a charge transfer transistor having a drain connected to a boosting node, a gate connected to a control node, a source connected to a high voltage generating terminal, and a substrate connected to a ground voltage. Usually, the charge transfer transistor includes a NMOS transistor to transfer the charges of the boosting node to the high voltage generating terminal in response to a voltage of the control node.
FIG. 1
is a circuit diagram of a conventional high voltage generating circuit. The conventional high voltage generating circuit comprises inverters I
1
, I
2
, I
3
and I
4
, NMOS capacitors C
1
, C
2
and C
3
and NMOS transistors N
1
to N
6
. Inverters I
1
and I
2
are supplied with a power supply voltage VCC, inverters I
3
and I
4
are supplied with a high voltage VPP, and the substrates of NMOS transistors N
1
to N
6
are supplied with a ground voltage.
In operation, inverter I
1
inverts a signal CON
1
, and inverter I
2
inverts the inverted output signal of inverter I
1
. Capacitor C
1
boosts the voltage at node A in response to an output signal from inverter I
1
, which is at VCC. NMOS transistor N
1
applies a voltage at node A equal to voltage VCC−Vth. The node A is initially at the level of VCC−Vth, and then is boosted from VCC−Vth to 2VCC−Vth, when VCC−Vth is boosted by capacitor C
1
. When the voltage at node A exceeds VCC+Vth, the NMOS transistor N
2
applies VCC to node B. The NMOS transistor N
3
adjusts the node B voltage to VCC−Vth. Capacitor C
2
boosts the voltage at node B in response to the output signal from inverter I
2
, at VCC. That is, the node B is initially at VCC−Vth, and is raised to VCC when the voltage at node A exceeds VCC+Vth. The voltage at node B is then boosted to 2VCC by the capacitor C
2
.
Inverter I
3
inverts a signal CON
2
, and inverter I
4
inverts the inverted output signal of inverter I
3
, which is at voltage VPP of a high voltage generating terminal. NMOS transistor N
4
applies VCC at node C, in response to the output signal at VPP from inverter I
3
. NMOS transistor N
5
adjusts node C voltage to VCC−Vth. Capacitor C
3
boosts the voltage at node C in response to the output signal (VPP) of inverter I
4
. Node C is initially at VCC−Vth, and becomes VCC when the output voltage of inverter I
3
exceeds VCC+Vth. Thus, the voltage at node C is boosted to VCC+VPP by capacitor C
3
. NMOS transistor N
6
is turned on in response to the voltage at node C, and a charge sharing operation between node B and the high voltage generating terminal VPP is performed. Hence, NMOS transistor N
6
may be referred to as a charge sharing transistor.
FIG. 2
is a signal waveform representing the voltage changes at each node in the circuit of FIG.
1
. As shown in
FIG. 2
, voltage Vth is a threshold voltage of each of the NMOS transistors N
1
to N
6
.
Initially, nodes A, B and C are precharged by the voltages 2VCC−Vth, VCC and VCC, respectively, when the signals CON
1
and CON
2
of a ground voltage level are applied to the high voltage generating circuit. Accordingly, when nodes A, B and C are supplied with CON
1
and CON
2
at VCC, the voltage of node A becomes VCC−Vth, the voltage at node C is boosted to VCC+VPP, and the voltage at node B is boosted to 2VCC. At the same time, since the voltage at node C equals VCC+VPP, NMOS transistor N
6
is turned on to share the charge between node B and the high voltage generating terminal VPP, thereby increasing the voltage of the high voltage generating terminal VPP.
Accordingly, the voltage of high voltage generating terminal VPP is increased during the charge sharing operation; thus the voltage difference between the source and the substrate of the NMOS transistor N
6
widens, resulting in an increase of the threshold voltage of NMOS transistor N
6
. However, the voltage at node C (supplied to the gale of the NMOS transistor N
6
) is fixed to voltage VCC+VPP. Thus, NMOS transistor N
6
is not able to sufficiently transfer the charges from node B to the high voltage generating terminal VPP.
In other words, the substrate of NMOS transistor N
6
becomes the ground voltage, and its source becomes the high voltage VPP (or 2VCC). Accordingly, the voltage difference between the source and the substrate becomes VPP (or 2VCC). Thus, the threshold voltage (Vth) of NMOS transistor N
6
increases by several hundred volts, as compared to the case where the voltage difference between the source and substrate is equal to zero. However, the voltage applied to the gate of NMOS transistor N
6
is maintained at VPP+VCC, resulting in a potential deterioration in transfer efficiency of the charge transfer transistor (i.e., NMOS transistor N
6
).
If the voltage difference between the source and substrate of NMOS transistor N
6
is substantially uniform or uniform, the Vth is not increased, and deterioration of the charge transfer efficiency of charge transfer transistor N
6
may be reduced. In other words, the charge transfer efficiency of the charge transfer transistor would not deteriorate if the voltage of the substrate is increased based on an increment of the voltage at the source.
When boosting the high voltage in a conventional high voltage generating circuit such as shown in
FIG. 1
, a threshold voltage of the NMOS transistor N
6
is increased according to an increment of the source voltage of the NMOS transistor N
6
, and the substrate of the transistor is fixed to the ground voltage. Thus, a threshold voltage of NMOS transistor N
6
in
FIG. 1
increases in proportion to an increase in a voltage difference between the substrate and source. At this time, if the gate voltage of the NMOS transistor N
6
is uniformly fixed, the NMOS transistors in
FIG. 1
are not able to transfer sufficiently transfer the charges of a boosting node (i.e., node B) to the high voltage-generating terminal (i.e., VPP).
Therefore, when-boosting high voltage in a conventional high voltage generating circuit, such as is shown in
FIG. 1
, the threshold voltage of the charge transfer transistor (i.e., NMOS transistor N
6
in
FIG. 1
) is increased according to a voltage difference between the substrate and the source. Accordingly, the conventional high voltage generating circuit cannot rapidly transfer charges of the boosting node (i.e., node B) to the high voltage generating terminal VPP.
SUMMARY OF THE INVENTION
Exemplary embodiments of the present invention are directed to a method and apparatus for generating a high voltage in a device. A boosting means precharges a first node, a second node and a substrate voltage of a charge transfer transistor. The charge transfer transistor may be configured to perform a charge sharing operation between the first node and a high voltage generating terminal based on a voltage at the second node. The first node may be boosted to a first voltage, and the substrate voltage may be increased based on a voltage at the high voltage generating terminal. The second node may be boosted to a second voltage different than the first voltage, and the substrate voltage may be increased based on a voltage at the high voltage generating terminal. The substrate voltage may also be increased based on changes to the first voltage of the first node that occur during the charge sharing operation performed by the charge transfer transistor.
REFERENCES:
patent: 6456150 (2002-09-01), Sacco et al.
patent: 6590440 (2003-07-01), Williams et al.
Harness Dickey
Samsung Electronics Co,. Ltd.
Zweizig Jeffrey
LandOfFree
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