Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2003-04-03
2004-05-25
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S300000, C713S322000, C713S600000, C713S601000, C713S500000, C713S503000, C331S00100A, C331S025000, C331S074000, C331S167000
Reexamination Certificate
active
06742132
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a clock signal generating circuit for a computing device, and more particularly, the present invention relates to a clock signal generating circuit for generating a ramped clock signal.
BACKGROUND OF THE INVENTION
Conventional computing systems utilize a clock signal generating circuit to provide timing information to a plurality of flip-flops. The flip-flops store binary states, such as 1's and 0's contingent on the absence or presence of a voltage or charge in the flip-flop. The binary states, read or written in the flip-flops, are then used for combinational boolean logic for operation and calculation procedures in the computing system. When writing a logic state in the flip-flop by a device external to the flip flop is desired, an oscillating voltage or clock signal operates the flip-flop to cause a voltage value representative of the stored state to be stored to be written to the latching circuit in the flip-flop, latch the voltage value and hold it available for reading devices external to the flip-flop. The clock signal is commonly a square wave that drives a gate of a transistor of the flip-flop. The clock signal generating circuit, external to the flip-flops, generates the signal to effectuate read, write and timing processes in the computing device. The square or abrupt signal drives the gates of transistors in the flip-flop to turn them ON and OFF in a relatively quick manner.
While this structure effectively allows a computing system to effectuate reading of stored logic states contained within the flip-flops, drawback exists. Specifically, only a portion of a computing system's flip-flops are actually read during any given read request. The remainder, however, still receive the clock signal. Commonly, the energy of the clock signal driving the unread flip-flops is dissipated therein, thereby creating energy inefficiencies and increased heat dissipation. When this dissipation effect is multiplied with the numerous flip-flops contained within a computing device, the overall efficiency of that computing device is compromised. The present invention was developed in light of these and other drawbacks.
SUMMARY OF THE INVENTION
A clock signal generating circuit includes an oscillator portion that sustains a ramped oscillating clock signal in a memory storage device electrically connected to the oscillator portion, a switch portion that supplements electrical energy to the oscillator portion, and a cycle controller connected to the oscillator portion and the switch portion to supplement energy to the oscillator portion when a peak voltage or current level of the clock signal falls below a predetermined value.
Other aspects of the invention will be apparent to those skilled in the art after reviewing the drawings and the detailed description below.
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Neil H.E. Weste and Kamran Eshraghian, “Principles of CMOS VLSI Design”, 1992, Addison-Wesely, p.(s): 10.*
Low-Power Digital Systems Based on Adiabatic-Switching Principles by William C. Athas, Lars “J.” Svensson, Member IEEE, Jeffrey G. Koller, Nestoras Tzartzanis, and Eric Ying-Chin Cho, Student Member, IEEE in the IEEE Transaction On Very Large Scale Integration (VLSI) Systems, vol. 2, No. 4, Dec. 1994.
A Resonant Clock Generator for Single-Phase Adiabatic Systems by Conrad H. Ziesler, Suhwan Kim and Marios C. Papaefthymiou. P)ublished ISLPED '01, Aug. 6-7, 2001.
Energy Recovering Static Memory by Joohee Kim, Conrad H. Ziesler & Marios C. Papaefthymiou. Published ISLPED '02, Aug. 12-14, 2002.
Papaefthymiou Marios C.
Ziesler Conrad H.
Lee Thomas
Rader & Fishman & Grauer, PLLC
The Regents of the University of Michigan
Trujillo James K
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