Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-12-11
2007-12-11
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S016000, C714S030000, C714S033000, C714S727000, C714S734000
Reexamination Certificate
active
11243713
ABSTRACT:
An aspect of the invention relates to a method, apparatus, and computer-readable medium for processing schematic data for an integrated circuit having a boundary scan architecture. A path through cells of the schematic data to generate a hierarchy of cells associated with a boundary scan chain. Each ignore cell in the hierarchy is pruned. Each short cell in the hierarchy is replaced with a direct connection. A shadow net is added to each net of the hierarchy. Each of the cells in the hierarchy is flattened in a bottom-up fashion.
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Roberts Mark B.
Roberts Scott K.
Brush Robert
Kik Phallaka
Xilinx , Inc.
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