Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2001-01-30
2002-09-24
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S233500
Reexamination Certificate
active
06456540
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to memory read circuits, and more specifically to sensing cell elements in a flash memory device.
BACKGROUND OF THE INVENTION
Semiconductor memory devices utilize large numbers of small storage elements, called “cells”, that are organized in regular arrays. Reading data stored in these storage elements is the function of decoding circuits and sense amplifiers. In a typical semiconductor memory, the row decoding circuits are labeled “X decoders” and the column decoding circuits are labeled “Y decoders.” When an address is supplied to the semiconductor memory device, the X decoders and Y decoders select the appropriate cell or cells which correspond to that particular address.
Referring now to
FIG. 1
, a schematic diagram of the read sensing circuits in a memory device is shown. The
FIG. 1
circuit shows an exemplary memory cell, flash cell
118
, in an “flash” electronically programmable read-only memory (EPROM). When properly biased, and when a positive voltage is applied to the gate of flash cell
118
, a current i
C
flows in the drain of flash cell
188
. The current i
C
will differ depending upon there being a logical “1” or “0” stored in flash cell
118
. Exemplary values are i
C
=10 microamps for a “
1
” and i
C
=30 microamps for a “0”.
In order to properly bias flash cell
118
for read sensing, a drain bias circuit
110
is employed. Flash cell
118
is selected when X decoders present X enable signal on X enable terminal
144
, and when the Y decoders present global Y (GY) enable signal on GY enable terminal
142
. When GY transistor
114
is turned on by GY enable signal, current can then flow from the drain bias circuit
110
first through sensing node (SEN node)
112
and thence through flash cell
118
. In the
FIG. 1
example, for the sake of clarity only one flash cell
118
is shown per column. Other similar devices (not shown) will be attached to the source of GY transistor
114
at global bit line (GBL)
116
.
Drain bias circuitry
110
includes a controlled resistance that converts the current i
C
into a voltage capable of being sensed by sense amplifier
130
. This voltage is supplied over sense input/read input (SIN/RIN) signal line
140
to one input
132
of sense amplifier
130
. A duplicate of the drain bias circuit
110
, flash cell
118
, and GY transistor
114
, drain bias circuit
120
, reference cell
128
, and dummy GY transistor
124
, respectively, provide a means for providing a dummy current, i
R
. These dummy circuits permit the construction of a standard reference voltage to be presented to alternate input
134
of sense amplifier
130
. In an exemplary case i
R
=20 microamps, halfway between the extremes of i
C
values.
Drain bias circuits
110
,
120
and sense amplifier
130
consume a large portion of the supply current of the memory device. Therefore many designs turn off sense amplifier
130
when not actually reading data. Similarly, drain bias circuits
110
,
120
may be disabled by placing cut-off transistors into the supply current path, preventing drain bias circuits
110
,
120
from consuming current when not actually reading data. However, placing such cut-off transistors within drain bias circuits may require making the cut-off transistors relatively large. Other shortcomings of such placement may include complexities of driving SEN node
112
.
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Intel Corp., “Boot Block Flash Memory: Understanding ATD Circuitry” support.intel.com/support/flash/memory/bootblock/24582.HTM, pp. 1-4, Sep. 8, 2000.
Intel Corp., “3-Volt Advanced and Boot Block Flash Memory” Order #290645-009, pp. 7-22 and 57, Apr. 24, 2000.
Baltar Robert
Trivedi Ritesh
Ho Hoai V.
Le Thong
Nicholls Dennis A.
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