Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2005-09-27
2005-09-27
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S023000, C710S039000, C710S052000, C711S156000, C370S232000, C370S413000
Reexamination Certificate
active
06950887
ABSTRACT:
An apparatus for gathering queue performance data includes an event conditioning logic unit that receives a queue enter signal, a queue exit signal, and a queue not empty signal from a queue. The apparatus also includes a counter that may be both incremented and decremented. The event conditioning logic unit may be programmed to increment the counter upon occurrences of a predetermined combination of the queue signals. The event conditioning logic unit may also be programmed to decrement the counter upon occurrences of an additional predetermined combination of the queue signals.
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Author: William Ford & William Topp, Title: “Data Structures with C++”, Date: 1996, Publisher: Prentice Hall, Pertinent pp: 204-208.
PCT International Search Report for PCT/US 02/14013, mailed Sep. 27, 2002.
Chapple James S.
Hady Frank T.
Mehta Kalpesh D.
Blakely , Sokoloff, Taylor & Zafman LLP
Gaffin Jeffrey
Intel Corporation
Patel Niketa
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