Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1997-12-08
2000-10-03
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
H03M 1300
Patent
active
06128761&
ABSTRACT:
This invention describes a test tool based on a PC workstation. This test tool is used to validate any E1 framing telecommunication device. In order to comply with the CCITT G.706 recommendations, a device has to pass a series of test cases that are predetermined. Each test case contains test sequences according to the CCITT G.706 specifications. The purpose of this test tool is to generate a set of stimuli in the transmission mode, whereas in the reception mode, the value of the data returned by the tested device is analyzed and compared with the expected response. The data bytes are structured as for E1 multiframe format containing 16 frames of 32 timeslots, where each timeslot is a data byte. According to the G.706 recommendations, timeslot 0 is dedicated to the frame and multiframe alignment and to the CRC test. The test tool enables generating of the content of the 8-bit timeslot 0 of each frame and therefore modifying the frame alignment, the multiframe alignment and the CRC procedure test tool; and storing the content of the received 8-bit timeslot 0 to monitor the remote alarm indication bit (`A` bit) reflecting the behavior of the tested device so as to determine whether this latter conforms to the CCITT G.706 recommendations.
REFERENCES:
patent: 5138608 (1992-08-01), Kucera et al.
patent: 5377209 (1994-12-01), Skinner et al.
patent: 5504753 (1996-04-01), Renger et al.
patent: 5621720 (1997-04-01), Bronte et al.
Benayoun Alain
Clara Jean-Louis
Cresp Jacques
Le Pennec Jean-Francois
Michel Patrick
Cady Albert De
Chase Shelly A
Cisco Technology Inc.
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