Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-07-30
2002-01-22
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S189070
Reexamination Certificate
active
06341094
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and apparatus for functional testing of memory related circuits. Such circuits include, for example, caches, memory controllers, memory management units (MMU's), and write-buffers. The invention is especially suitable for testing such circuits at the circuit design level, i.e. prior to the circuit being fabricated in an integrated circuit.
BACKGROUND TO THE INVENTION
At the design stage for an integrated circuit, a circuit design is typically represented as circuit data in a hardware description language (HDL). From the HDL, the circuit design can be mapped (through suitable processing) into an actual hardware design for fabrication in an integrated circuit. IEEE standards exist for HDLs, such as Verilog (IEEE standard 1364) and VHDL (IEEE standard 1076-1993).
The testing of circuit designs prior to fabrication in an integrated circuit is referred to in the art as verification, and represents an important step in the design process for an integrated circuit. With the complexity of circuits increasing continuously, it is impossible to guarantee the proper operation of a design without undergoing an extensive prior verification of the design.
One part of verification is functional verification, which focuses on testing whether a design behaves as it is supposed to from a functional point of view. In digital designs, this is usually done by testing the HDL model in a virtual testbench environment using a computer. This principle of functional verification using its data model is well known to the skilled man.
FIG. 1
illustrates a typical circuit arrangement for a cache circuit
10
, and
FIG. 2
illustrates a conventional virtual testbench for functional verification of the design of the cache using its design (HDL) model
10
′. As is known the skilled man, a cache
10
comprises a small fast memory with additional control logic, and is used to reduce the effective access time of a slower memory
12
addressed by a microprocessor (CPU)
14
. The cache
10
is typically coupled between the slower memory (or memory to be cached, also referred to herein as the “cached memory”)
12
and the CPU
14
, and the memory within the cache
10
stores portions of the data stored also in the slower memory
12
, ideally the most frequently accessed data. When the CPU addresses data that is currently held in the cache
10
, this is referred to as a cache-hit. In such a case, the cache
10
services the access and suppresses the access to the slower memory
12
. As the cache
10
can handle the access faster than the slower memory
12
, the CPU saves wait-states whenever a cache-hit occurs, leading to higher system performance.
Referring to
FIG. 2
, the virtual testbench environment
16
is defined in a host computer apparatus
18
. In the virtual testbench environment, at least the cache
10
′ and the slow memory
12
′ are represented by HDL data. Patterns of virtual test signals are applied to the cache model
10
′ to simulate read and write accesses, and the reactions of the cache model
10
′ are recorded. By analysing the behaviour of the cache model
10
′, and analysing the data in the cache and in the memory, the functionality of the cache can be verified.
The model may describe the circuit at various levels of detail or abstraction. A more abstract model may define the merely the behaviour of the circuit as a whole, rather than of part of the circuit. A more detailed model may describe the functionality of parts of the circuit and the dataflow in the circuit, and may be partly or wholly synthesisable in hardware. However, the more detailed the model, the slower it is to test. Therefore, tests are normally carried out progressively, starting with the fast (abstract) model, and progressing through other models if each functional verification passes its tests.
In one form, the cache model
10
′ is driven either by hard-coded stimuli, or by a bus functional model which can simulate different bus accesses to the cache. After simulation, the developer has to analyse the cache behaviour and the memory contents manually, which is laborious and very time-consuming.
In another form, the CPU
14
is incorporated in the testbench as a model represented by HDL data. The person developing the circuit can then write code which is “executed” on the CPU-model and tests the cache model
10
′. Although the code “running” on the CPU-model can help to identify incorrect operation of the cache model
10
′ to a certain extent, it cannot identify an exact time of occurrence of a cache error in view of the program execution overhead. In other words, the software cannot monitor immediately each access which it creates. Hence there is a variable time delay from the point in time when an error occurs, and the point in time at which this can be detected by software on the same CPU
14
. In addition, such a semi-automatic method of analysis slows the simulation significantly.
A further aspect which slows verification for both of the above techniques is the required loading and unloading of data to and from the cached memory model
12
′. Before the verification process can begin, the memory model
12
′ has to be loaded with predetermined data, so that the memory model
12
′ has a desired known state before the test. Also, the complete contents of the memory model
12
′ have to be unloaded for analysis after the test, so that the operation of the cache model
10
′ can be fully verified. Such loading and unloading of data has to be performed through the cache model
10
′ with the cache held in a de-activated state. Each data transfer operation is time consuming, and the need for two transfers (one for loading, one for unloading) slows the verification process considerably.
SUMMARY OF THE INVENTION
The invention concerns an apparatus for testing a functional operation of a memory related circuit. The memory related circuit may be represented by a first circuit model defining a circuit under test. The apparatus may comprise a storage device and a processor. The storage device may be configured for storing the first circuit model representing the circuit under test, and for storing a second circuit model. The second circuit model may represent a testbench circuit for interfacing with the circuit under test, and may include a first memory and monitor circuitry. The first memory may be configured for interfacing with a first port of the circuit under test. The monitor circuitry may be configured for interfacing with at least one of the memory and a second port of the circuit under test, for monitoring the response of the circuit under test as simulated signals are applied thereto. The processor may be configured for processing the first and second circuit models to simulate the response of the circuit under test when the simulated signals are applied thereto via the testbench circuit. The simulated signals may simulate read and write accesses to the circuit under test.
The objects, features and advantages of the invention include providing an arrangement which can verify the functionality of the circuit under test (i) in near real time, simultaneously with the stimulation of the circuit under test, (ii) without requiring software overhead for a stimulator CPU model, (iii) automatically without requiring unloading of a memory merely to verify the functionality, and (iv) optionally with a similar reference model to provide a direct comparison of expected internal circuit behaviour and expected internal signals.
REFERENCES:
patent: 4249250 (1981-02-01), Scowen et al.
patent: 4584663 (1986-04-01), Tanikawa et al.
patent: 4718042 (1988-01-01), Moll et al.
LSI Logic Corporation
Maiorana Christopher P.
Tran Andrew Q.
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