Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Patent
1995-01-27
2000-01-11
Heckler, Thomas M.
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
39550005, G06F 104, G06F 1100
Patent
active
060147520
ABSTRACT:
A clock generation and control circuit to debug an integrated circuit includes a multiplexer connected to a set of input lines that carry a set of clock signals. The multiplexer selects one of the input lines in response to a select signal generated by a decode circuit. A control circuit provides input signals to the decode circuit. The control circuit specifies a disabled output clock signal in response to a stop signal applied to a single external pin of the integrated circuit. Alternately, the control circuit specifies a disabled output clock signal through a test access port of the integrated circuit. Debug operations are executed while the output clock signal is disabled.
REFERENCES:
patent: 5179696 (1993-01-01), Shouda
patent: 5253255 (1993-10-01), Carbine
patent: 5394403 (1995-02-01), Klein
Holdbrook, et al, "MicroSPARC: A Case-Study of Scan Based Debug", International Test Conference, Washington, D.C., Oct. 1994, pp. 70-75.
IEEE Standard Test Access Port and Boundary Scan Architecture, IEEE Std. 1149.1-1990.
Bhabuthmal Kanti
Hao Hong
Heckler Thomas M.
Sun Mircosystems, Inc.
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