Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2002-10-15
2004-07-20
Tan, Tibol (Department: 2819)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S721000, C714S724000, C714S725000, C714S726000, C326S016000, C326S037000, C326S046000
Reexamination Certificate
active
06766484
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to techniques for characterizing the performance of electronic circuits. More specifically, the present invention relates to a method and an apparatus for fully characterizing the propagation delay through an n-input circuit.
2. Related Art
As electronic circuits become increasingly faster, timing margins for signals passing through these circuits are becoming progressively tighter. It is consequently becoming more important to be able to fully characterize the propagation delay through elements within these circuits to ensure that the circuits function properly.
Characterizing the propagation delay through an electronic circuit typically involves: (1) establishing a voltage level for each input to the circuit; (2) changing the voltage level for at least one input; and then (3) measuring the delay until related changes appear at the output to the circuit. Note that each input pattern can cause a different propagation delay. Moreover, the propagation delay for a transition from a low voltage to a high voltage can be different from the propagation delay for a corresponding transition from a high voltage to a low voltage. Additionally, simultaneous transitions on two or more inputs can affect the propagation delay. Hence, as the number of inputs to a circuit grows, it becomes increasingly more difficult to ensure that all possible combinations have been tested.
Hence, what is needed is a method and an apparatus that characterizes the propagation delay through an electronic circuit in a manner that ensures that every possible transition is tested.
SUMMARY
One embodiment of the present invention provides a system that facilitates fully characterizing propagation delay through an n-input circuit. The system operates by first receiving the n-input circuit. Next, the system establishes programmable voltage sources at each input of the n-input circuit. The system then programs each programmable voltage source to provide a sequence of input patterns to the n-input circuit. This sequence includes the 2
2n
possible transitions between all possible pairs of input patterns. Next, the system measures the propagation delay between the input and the output of the n-input circuit for each transition in the sequence of input patterns and then reports the results.
In a variation of this embodiment, the n-input circuit can be either a simulated circuit or a physical circuit.
In a further variation, measuring the propagation delay involves recording a minimum delay and a maximum delay between the input and the output of the n-input circuit for each transition in the sequence of input patterns.
In a further variation, each programmable voltage source outputs a first voltage level at a first time and a second voltage level at a second time, with the first voltage level being independent of the second voltage level. Moreover, the first voltage level and the second voltage level can each be set to either a low voltage or a high voltage.
In a further variation, the system provides the sequence of input patterns by first creating separate binary variables representing the first voltage level and the second voltage level for each input of the n-input circuit. The system then changes values of the binary variables in a sequence that ensures that each of the 2
2n
possible transitions is created.
REFERENCES:
patent: 5905403 (1999-05-01), Gillette
patent: 6173424 (2001-01-01), Voshell et al.
patent: 6479985 (2002-11-01), Lambert
Grundler Edward J.
Park Vaughan & Fleming LLP
Sun Microsystems Inc.
Tan Tibol
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