Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2006-11-16
2009-12-29
Song, Jasmine (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S123000, C711S126000, C711S154000, C711S169000, C712S208000, C712S225000
Reexamination Certificate
active
07640414
ABSTRACT:
Methods, systems, and computer program products for forwarding store data to loads in a pipelined processor are provided. In one implementation, a processor is provided that includes a decoder operable to decode an instruction, and a plurality of execution units operable to respectively execute a decoded instruction from the decoder. The plurality of execution units include a load/store execution unit operable to execute decoded load instructions and decoded store instructions and generate corresponding load memory operations and store memory operations. The store queue is operable to buffer one or more store memory operations prior to the one or more memory operations being completed, and the store queue is operable to forward store data of the one or more store memory operations buffered in the store queue to a load memory operation on a byte-by-byte basis.
REFERENCES:
patent: 5606670 (1997-02-01), Abramson et al.
patent: 6141747 (2000-10-01), Witt
patent: 6393536 (2002-05-01), Hughes et al.
Cox Jason Alan
Lin Kevin Chih Kang
Robinson Eric Francis
International Business Machines - Corporation
McBurney Mark E.
Song Jasmine
Yee & Associates P.C.
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