Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
1999-07-22
2002-03-05
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S114000, C438S118000, C438S612000, C257S758000, C257S783000, C257S778000, C257S779000
Reexamination Certificate
active
06352881
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to flip chip packaging for integrated circuits. More particularly, it relates to flip chips that have an integral layer of underfill material and to methods for making such flip chips.
BACKGROUND OF THE INVENTION
There are a number of conventional processes for packaging integrated circuits. One approach which is commonly referred to as “flip chip” packaging generally contemplates forming solder bumps (or other suitable contacts) directly on I/O pads formed on an integrated circuit die. The die is then typically attached to a substrate such as printed circuit board or package substrate such that the die contacts directly connect to corresponding contacts on the substrate. That is, the die is placed on the substrate with the contact bumps facing corresponding contacts on the substrate. The solder contact bumps are then reflowed to electrically connect the die to the substrate.
When a flip chip is attached to the substrate, an air gap typically remains between flip chip and substrate. This gap is commonly filled with material that is flowed into the gap in liquid form and is then solidified. This material is generally a mixture of a resin and small silica spheres and is generally called underfill. The underfill material is typically applied in liquid form from a dispenser at one edge of a flip chip. The material then flows into the narrow gap and spreads across the flip chip until finally the entire area of the gap between flip chip and substrate is filled.
There are problems associated with underfill. For example, the operation of applying underfill must be repeated for each flip chip. Repeating such an operation many times adds to the cost of manufacture. Also, as the underfill material flows past solder bumps to fill the gap, separation of glass from resin may occur. The separation of silica spheres from the resin occurs as some silica spheres become trapped as they meet solder ball obstacles. The underfill material will develop streaks of high and low silica concentration. The silica may also separate from the resin by sinking to one side of the gap, thus creating a silica rich side in the bottom and a resin rich side on the top of the gap. This segregation of silica and resin alters the mechanical properties of the filled region and thereby negates the mechanical function of the underfill.
Therefore there is a need for a lower cost underfill application process and there is a need to reduce the amount of silica segregation that occurs.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects and in accordance with the purpose of the present invention, methods for forming a layer of underfill adhesive on an integrated circuit located on an active surface of a wafer are disclosed. In one embodiment, the integrated circuit has solder bumped electrically conductive pads. A layer of underfill adhesive is deposited on the active surface of the wafer in such a way that at least a portion of most of the solder balls remain uncovered. The deposited layer of underfill adhesive is then partially cured.
In a preferred embodiment, the integrated circuit is a singulated flip chip that is mounted on a substrate by directly aligning selected ones of solder bumped flip chip bond pads to corresponding substrate bond pads. The flip chip is electrically connected to the substrate by a solder reflow operation that also finally cures the underfill adhesive.
In another embodiment, a flip chip integrated circuit package is disclosed. The flip chip integrated circuit package includes a substrate having a plurality of substrate bond pads suitable for being electrically coupled to external circuitry. The flip chip integrated circuit package also includes a flip chip integrated circuit having flip chip bond pads. Some of flip chip bond pads have solder balls and are directly aligned to and in direct contact with corresponding substrate bond pads by way of the associated reflowed solder balls. A substantially uniform layer of underfill adhesive is juxtaposed between the substrate and the flip chip integrated circuit.
In yet another embodiment, an apparatus for forming a layer of underfill adhesive on an integrated circuit having electrically conductive pads located on an active surface of a wafer is disclosed. The apparatus includes a means for forming a solder ball on most of the electrically conductive pads and a means for forming the layer of underfill adhesive on the active surface of the wafer, wherein at least some portion of most of the solder balls remain uncovered. The apparatus also includes a means for partially curing the underfill adhesive and a means for singulating the integrated circuit. The apparatus also includes a means for reflowing the solder balls such that the reflowing fully cures the underfill adhesive.
In still another embodiment of the invention, a method for forming a layer of underfill adhesive on an integrated circuit is described. A solder ball is formed on most of the electrically conductive pads included on an active surface of the integrated circuit. A layer of underfill adhesive is then formed on the active surface of the integrated circuit such that at least some portion of most of the solder balls remain uncovered. The layer of underfill adhesive is then partially cured. The underfill adhesive is finally cured during a subsequent solder reflow operation.
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Kelkar Nikhil
Nguyen Luu
Prabhu Ashok
Quentin Christopher
Takiar Hem P.
Beyer Weaver & Thomas LLP
Fahmy Wael
National Semiconductor Corporation
Toledo Fernando
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