Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-02-27
2002-12-17
Phan, Trong (Department: 2834)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S236000
Reexamination Certificate
active
06496437
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory that must be periodically refreshed. More specifically, the present invention relates to a method and apparatus for performing refresh operations in a semiconductor memory during idle cycles of the memory.
DISCUSSION OF RELATED ART
Some conventional semiconductor memories, such as dynamic random access memory (DRAM), must be periodically refreshed in order to retain valid data. During refresh operations, external access typically is not allowed. In addition, a mechanism is required to inform the memory controller that the DRAM is performing a refresh operation. Any pending memory transaction has to be delayed until the refresh operation is completed. Refresh operations therefore lengthen the overall access time for memory accesses. It is therefore important to design a memory system in which the impact of refresh operations on external memory access is minimized.
Many different methods have been proposed to refresh these semiconductor memories. In one of these methods, which is commonly referred to as “CAS before RAS,” an external device signals a refresh operation by asserting a column access signal CAS# prior to asserting a row access signal RAS#. During normal accesses, the column address strobe signal RAS# is asserted before the column address strobe signal CAS#. In response to detecting the “CAS before RAS” condition, the memory performs a refresh operation. The refresh operation typically is performed by reading the row of the memory to be refreshed. A “CAS before RAS” refresh scheme is described in 1991 Memory Products Data Book, uPD424248 262,144×4-Bit Dynamic CMOS RAM, NEC Electronics, pp 6-101 to 6-113. This reference also illustrates a hidden refresh that is a variation of the “CAS before RAS” refresh method. These methods for refresh require handshake communication between the semiconductor memory and the external device, making the external device control the memory refresh.
Another conventional semiconductor memory that must be periodically refreshed is synchronous DRAM (SDRAM). One conventional SDRAM initiates refresh operations in response to control signals (i.e., RAS#, CAS#, CS#, WE# and CKE) received from an external device. These control signals are decoded to provide command codes that are used to control the refresh operations of the SDRAM. For example, when the control signals RAS#, CAS#, CS#, WE# and CKE have values of 0,0,0,1, and 1, a control code for initiating an auto refresh operation is generated. Similarly, when those same control signals have values of 0,0,0,1, and 0, a control code for initiating a self refresh operation is generated. This SDRAM is described in more detail IBM0316409C, 16 Mbit Synchronous DRAM data sheet, 1996, IBM Corporation.
Other synchronous DRAM have used explicit command codes for handling memory refresh. These include SLDRAM [4M=18 SLDRAM CONS400.P65—Rev. Sep. 22, 1997, 400 Mb/s/pin SLDRAM SLD4M18DR400 4M=18 SLDRAM Data Sheet, SLDRAM Consortium] and Rambus DRAM (RDRAM). [Direct Rambus Technology Disclosure, Oct. 15, 1997, Rambus Inc.] All of the above-described command codes are generated by the external device, and must be communicated to the memory device, thereby complicating the interface to the semiconductor memory. The interface then becomes incompatible with the interface of a simpler device, such as an SPAM.
Other conventional DRAM refresh schemes incorporate a dedicated refresh control signal. These schemes are exemplified by enhanced DRAM (EDRAM) [DM2202/2212 EDRAM, 1 Mb×4 Enhanced Dynamic RAM, 1994, Ramtron International Corporation] and cache DRAM (CDRAM) [Dosaka et. al, U.S. Pat. No. 5,559,750]. In both the EDRAM and the CDRAM, a dedicated external refresh signal is used to initiate refresh operations. As noted with the external signals of the aforementioned devices, this additional external signal is incompatible with an SRAM and other simple interface devices.
Schemes for performing refresh operations during unused idle memory cycles of a DRAM are described in U.S. Pat. No. 6,078,547 entitled “Method And Structure For Controlling Operation Of A DRAM Array”, U.S. Pat. No. 6,028,804 entitled “Method And Apparatus For 1-T SRAM Compatible Memory”, U.S. Pat. No. 5,999,474 entitled “Method And Apparatus For Complete Hiding Of The Refresh Of A Semiconductor Memory”, and U.S. Pat. No. 6,075,740 entitled “Method And Apparatus For Increasing The Time Available For Refresh For 1-T SRAM Compatible Devices”, all by the present inventor.
SUMMARY
Accordingly, the present invention provides a memory system having a memory controller and one or more memory blocks that are commonly coupled to a system bus. Each memory block includes an array of memory cells that must be periodically refreshed to retain valid data. Each memory block also includes a refresh control circuit that refreshes the memory cells during idle cycles of the memory array.
The memory controller includes a refresh manager that monitors the number of idle cycles on the system bus during a refresh period, and forces one or more idle cycles on the system bus if the monitored number of idle cycles is less than a predetermined number of idle cycles during the refresh period. For example, in one embodiment, the refresh period for eight rows of memory cells is 20.48 microseconds. If the refresh manager detects fewer than eight idle cycles on the system bus during the 20.48 microsecond refresh period, then the refresh manager forces the appropriate number of idle cycles onto the system bus at the end of the refresh period. For example, if the refresh manager only detects six idle cycles on the system bus during the refresh period, then the refresh manager will force two additional idle cycles on the system bus at the end of the refresh period. As a result, eight idle cycles are provided on the system bus. Each of the memory blocks performs a pending refresh operation during an idle cycle on the system bus. As a result, the eight rows of memory cells are always refreshed within eight cycles of the end of the refresh period (or shorter). There is a relatively high probability that the refresh manager will not have to force any idle cycles at the end of the refresh period. Moreover, even if idle cycles must be forced, the maximum time required for these idle cycles represents a small fraction of the refresh period (e.g., 0.4 percent).
While idle cycles are being forced, the refresh manager asserts a control signal that informs accessing clients of the memory system that memory accesses must be deferred. After the idle cycles have been forced, the refresh manager de-asserts the control signal to inform the accessing clients that memory accesses can proceed.
In a particular embodiment, the refresh manager includes an idle cycle counter for counting the number of idle cycles on the system bus. When the number of idle cycles on the system bus is equal to the predetermined number of idle cycles, the idle cycle counter generates a FULL signal. A refresh counter is coupled to receive the FULL signal. If the refresh counter determines that the refresh period expires prior to receiving the FULL signal from the idle cycle counter, then the refresh counter asserts a control signal that forces idle cycles on the system bus. If the refresh counter receives the FULL signal prior to the expiration of the refresh period, the refresh counter is reset, thereby beginning a new refresh period.
Within each memory block, an access arbiter receives external access requests (which are initiated by the memory controller) and refresh requests (which are generated within the memory block). The access arbiter always grants priority to any pending external access request. The access arbiter will allow refresh requests to be granted only if there are no pending external access requests. As a result, the refresh requests do not impede the external access requests. The refresh operations are performed during
Bever Hoffman & Harms LLP
Hoffman E. Eric
Monolithic Systems Technology, Inc.
Phan Trong
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