Method and apparatus for folding and laying out electronic...

Details Method and apparatus for folding and laying out electronic... Method and apparatus for folding and laying out electronic...

2007-03-13

2007-03-13

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10856502

ABSTRACT:
A method and apparatus folds a circuit having a plurality of transistors. The folding includes: (a) determining a number of folds to realize a desired layout of the circuit based on a netlist of the circuit, a folded circuit having a number of fingers corresponding to the number of folds; (b) creating a single-finger layout for the circuit, the single-finger layout including a respective smaller transistor for each of the original transistors, each of the smaller transistors having a size which is an original size of the corresponding original transistor divided by the number of the fingers, the smaller transistors in the single-finger layout having an arrangement the same as an original arrangement of the original transistors in the circuit; and (c) tiling the single-finger layout for the number of folds such that each single-finger layout abuts an adjacent single-finger layout.

REFERENCES:
patent: 3999214 (1976-12-01), Cass
patent: 2004/0078768 (2004-04-01), McGuinness et al.
A. Gupta et al., “Optimal 2-D Cell Layout with Integrated Transistor Folding”, 1998 ACM Intel Corporation, pp. 1-8.
J. Kim et al., “An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design”, Association for Computing Machinery, Inc., 1997, pp. 1-4.

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