Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-02
2007-10-02
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
11030352
ABSTRACT:
To fix hold time violations, timing analysis is initially performed on a circuit design for each set of timing constraints to determine a setup slack and a hold slack for each signal path for that set of timing constraints. The slack for a signal path indicates the amount of timing margin or the amount of timing violation for that signal path. Signal paths with hold time violations (or “hold paths”) are identified and retained, and other signal paths without hold time violations are discarded. For each hold path, signal paths with at least one node in common with the hold path (or “related setup paths”) are identified and retained. Related setup paths with large setup slacks may be pruned. The hold time violations for the hold paths are then fixed based on the hold slacks for the hold paths and the setup slacks for the related setup paths.
REFERENCES:
patent: 5764528 (1998-06-01), Nakamura
patent: 5896299 (1999-04-01), Ginetti et al.
patent: 6591407 (2003-07-01), Kaufman
patent: 6651224 (2003-11-01), Sano et al.
patent: 6701505 (2004-03-01), Srinivasan
patent: 6886147 (2005-04-01), Johnson et al.
patent: 6990645 (2006-01-01), Lichtensteiger et al.
patent: 6990646 (2006-01-01), Yoshikawa
patent: 2001/0007144 (2001-07-01), Terazawa
patent: 2003/0101399 (2003-05-01), Yoshikawa
patent: 2004/0139410 (2004-07-01), Ghameshlu et al.
Kuetzer, Kurt, et al.; “Is Redundancy Necessary to Reduce Delay?”; IEEE Apr. 1991; New York, NY; pp. 427-435.
Shenoy, Narendra, et al; “Minimum Padding to Satisfy Short Path Constraints”; IEEE 1993; Berkeley, CA; pp. 156-161.
Singh, Kanwar Jit, et al; “Timing Optimization of Combinational Logic”; IEEE 1998; Berekeley, CA; pp. 282-285.
Kim, Ki-Wook, et al; “Coupling-Aware Minimum Delay Optimisation for Domino Logic Circuits”; Electronics Letters; Jun. 21, 2001; vol. 37, No. 13, no page numbers.
Becer, Murat, et al; “Crosstalk Noise Control in an SoC Physical Design Flow”; IEEE Apr. 2004; Austin, TX; pp. 488-497.
Chen Chih-Tung (Tony)
Gong Jie
Sun Yigang
Garbowski Leigh M.
QUALCOMM Incorporated
Rouse Thomas R.
Seo Howard H.
LandOfFree
Method and apparatus for fixing hold time violations in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for fixing hold time violations in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for fixing hold time violations in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3885571