Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2006-10-17
2006-10-17
Cao, Chun (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S600000, C327S141000
Reexamination Certificate
active
07124314
ABSTRACT:
An IC including skew-programmable clock buffers, fixed skew logic circuit, an external interface and a skew controller. Each skew-programmable clock buffer receives a distributed clock signal and provides a corresponding local clock signal having a programmed skew. The fixed logic circuit enables permanent programming of static skew values and the external interface enables programming of dynamic skew values. The skew controller selects between the static and dynamic skew values and programs the skew-programmable clock buffers based on selected skew values. In one embodiment, the skew controller is operative to detect a skew over-ride command upon reset of the IC and to select between the static and dynamic skew values based on the skew over-ride command. The programmable memory may be integrated on the IC or externally coupled via the external interface. The fixed skew logic circuit is implemented as any type of permanent programmable block, such as laser-blown fuses, an EPROM, etc.
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Hariharan Suresh
Ho Stanley
Lundberg James R.
Cao Chun
Huffman James W.
Huffman Richard K.
IP-First LLC
Stanford Gary R.
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