Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2011-04-12
2011-04-12
Stoynov, Stefan (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S400000, C713S600000, C326S093000, C327S100000, C375S354000, C377S027000, C702S124000, C709S214000, C710S058000, C711S005000, C711S167000
Reexamination Certificate
active
07925912
ABSTRACT:
A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more first memory cells and a second memory circuit also having two or more second memory cells. The first memory circuit may be configured to periodically sample the reference pulse at the rising edges of a first sample clock while the second memory circuit may be configured to periodically sample the reference pulse at the falling edges of the first sample clock. A combinatorial logic circuit may also be included to produce the output pulse having at least one adjusted edge based on a set of timing instructions and timing information provided by the first and/or second memory circuits.
REFERENCES:
patent: 4821295 (1989-04-01), Sanner
patent: 5742188 (1998-04-01), Jiang et al.
patent: 7015726 (2006-03-01), Tayler et al.
patent: 7698588 (2010-04-01), Boerstler et al.
Keithley Douglas G.
Moss Roy G.
Woolley Richard N.
Marvell International Ltd.
Stoynov Stefan
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