Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-02-21
2006-02-21
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07003739
ABSTRACT:
The present invention is directed to a method and apparatus to find an optimal unification substitution for formulas in a technology library. In an exemplary aspect of the present invention, a method for finding an optimal unification substitution for formulas in a technology library during integrated circuit design may include the following steps: (a) receiving input including a list L of pairs of formulas in standard form, a set S of substitutions for variables, a right part e(x1, . . . , xp) of an identity, and an information I={t, h, r, a, p} on best application; (b) when the list L is not empty, extracting and removing first pair (ƒ′(A′1, . . . , A′n′), g′(B′1, . . . , B′m′)) from the list L; (c) removing head inverters and buffers from formulas ƒ′(A′1, . . . , A′n′) and g′(B′1, . . . , B′m′)) and obtaining a pair (ƒ(A1, . . . , An), g(B1, . . . , Bm)); (d) when the ƒ is a commutative operation but neither a variable nor constant, and when heads of the formulas ƒ(A1, . . . , An) and g(B1, . . . , Bm) are equal, searching for a basic argument Ajof the formula ƒ(A1, . . . , An); (e) when the basic argument Ajis found, letting P be head of said Ajand setting i=1; (f) when head of Biis equal to the P, making copy L′ of the list L and making copy S′ of the set S; and (g) forming a reduced pair (A′, B′) for pairs (ƒ(A1, . . . , An), ƒ(B1, . . . , Bn)) and (Aj, Bi) and adding the pairs (Aj, Bi) and (A′, B′) to the list L′.
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Galatenko Alexei V.
Gasanov Elyar E.
Podkolzin Alexander S.
LSI Logic Corporation
Siek Vuthe
Suiter - West - Swantz PC LLO
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