Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-01-25
2005-01-25
Moazzami, Nasser (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C712S207000
Reexamination Certificate
active
06848030
ABSTRACT:
A processing system has a processor, a cache, and a fetch unit. If there is a miss in the cache, the fetch unit generates a fetch address for the miss in the cache for the purpose of retrieving the requested data from external memory and providing the data to the processor and loading the data in a location in a line in the cache. The fetch unit also generates additional prefetch addresses for addresses consecutive with the fetch address. The prefetch addresses continue to be generated for all of the locations in the line in the cache that are consecutive with the fetch address. The generation of prefetch addresses will be stopped if another requests arrives that is not part of the already generated prefetched addresses. Further, the outstanding prefetches will be terminated if the external memory can handle such termination.
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Efrat Jacob
Gur Amit
Schupper Doron
Tokar Yakov
Clingan, Jr. James L.
Freescale Semiconductor Inc.
Moazzami Nasser
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