Method and apparatus for fault tolerant BIOS addressing

Details Method and apparatus for fault tolerant BIOS addressing Method and apparatus for fault tolerant BIOS addressing

1997-07-10

1998-08-18

Voeltz, Emanuel Todd

395651, 395653, 39518312, G06F 128

Patent

active

057970238

ABSTRACT:
An apparatus is described to provide a fault tolerant power-on of a computer system, using a BIOS memory containing a primary power-on system level configuration program for a computer system and a separate memory which contains a subset of the primary power-on system level configuration program. The subset program is accessed automatically, without human intervention, responding to a checksum detector of the BIOS memory data.

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