Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
2005-10-14
2008-11-04
Peyton, Tammara R (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C710S069000, C710S070000, C711S118000, C711S170000
Reexamination Certificate
active
07447814
ABSTRACT:
A method and apparatus for compressing uncompressed data by applying a transform prior to the application of a data compression scheme. At decompression time, a transform can be applied after a data decompression scheme has been applied to compressed data.
REFERENCES:
patent: 6795897 (2004-09-01), Benveniste et al.
“Adaptive Cache Compression for High-Performance Processor,” by Alaa R Alameldeen and David A. Wood, pp. 1-12, Jun. 19-23, 2004, http://www.cs.wisc.edu/multifacet/papers/isca04—adaptive—compression.pdf.
“Design and Performance of a Main Memory Hardware Data Compressor”, Morten Kjelso, Mark Gooch, Simon Jones; Electronic Systems Design Group, Loughborough University, Proceedings of Euromicro-22 IEEE 1996□□.
Publication: “A Block-sorting Lossless Data Compression Algorithm” by Michael Burrows and David Wheeler, published by the Digital Systems Research Center, May 10, 1994.
Publication: “Compressed Caching and Modem Virtual Memory Simulation”, by S.F. Kaplan, University of Texas at Austin, Dec. 1999.
Park Vaughan & Fleming LLP
Peyton Tammara R
Sun Microsystems Inc.
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