Method and apparatus for fast lock time

Details Method and apparatus for fast lock time Method and apparatus for fast lock time

1995-03-22

1997-03-18

Chin, Wellington

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327156, 331 18, H03D 324

Patent

active

056129807

ABSTRACT:
A system and method for fast frequency locking are provided in which the phase difference between first and second synchronization signals is measured (22). The frequency difference between the two signals is then determined (24). The frequency of the second synchronization signal is then set to that of the first synchronization signal (26). Thereafter, the feedback loop of a phase-locked loop circuit is closed, with an error signal representative of the phase difference between the first and second synchronization signals being offset by an amount equal to an error signal generated when the frequency of the second synchronization signal is set to that of the first synchronization signal.

REFERENCES:
patent: 3921095 (1975-11-01), Chu
patent: 4272729 (1981-06-01), Riley, Jr.
patent: 4418318 (1983-11-01), Swagerty et al.
patent: 4498059 (1985-02-01), Edwards et al.
patent: 5168245 (1992-12-01), Koskowich
European Search Report Application No. EP 96 10 4044 dated Jun. 28, 1996 by Examiner Van den Berg, J.G.J.
1979 International Symposium on Circuits and Systems Proceedings, IEEE Catalog No. 79 CH1421-7 CAS, Jul. 17-19, 1979 Hotel Pacific Tokyo, Japan.

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