Method and apparatus for fast evaluation of dynamic CMOS logic c

Details Method and apparatus for fast evaluation of dynamic CMOS logic c Method and apparatus for fast evaluation of dynamic CMOS logic c

1996-05-20

1998-10-20

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 17, 326 97, H03K 1901, H03K 1900

Patent

active

058252088

ABSTRACT:
According to the present invention, a domino CMOS logic circuit having a plurality of stages for evaluating logic signals is provided. In one embodiment, the domino CMOS logic circuit includes at least one stage which has a logic block that includes a plurality of logic devices, inputs and outputs, and a precharge/evaluate circuit. In a more specific embodiment, the circuit includes a first transistor having a source connected to a supply voltage, a gate connected to a delayed clock signal, and a drain, a second transistor having a source connected to the drain of the first transistor, a gate connected to a clock signal, and a drain connected to the outputs of the logic block.

REFERENCES:
patent: T926003 (1974-09-01), Nomiya et al.
patent: 4554570 (1985-11-01), Jastrzebski et al.
patent: 5263173 (1993-11-01), Gleason
patent: 5324673 (1994-06-01), Fitch et al.

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