Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-10-16
1998-08-11
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711100, 395845, 364DIG1, 3642423, 364DIG2, G06F 1300
Patent
active
057940703
ABSTRACT:
A computer system comprises a direct memory access (DMA) transfer unit and a plurality of DMA devices coupled by an external bus. The DMA transfer unit effectuates DMA transfers for the plurality of DMA devices. The DMA transfer unit contains a DMA controller, a bus arbiter, and a bus controller. The DMA controller and the bus controller generate a two-clock cycle DMA transfer. To effectuate a two-clock cycle DMA transfer, a requesting DMA device sets-up a DMA transfer with the DMA controller such that a DACK# signal is asserted during a first clock period. During a second clock period, the DMA controller sets-up the memory address. During a third clock period, the bus controller transitions a command signal on the external bus. Upon assertion of the command signal, valid data is asserted on the external bus. For demand and block mode operations, additional DMA transfers are executed in a two-clock cycle DMA transfer. The DMA controller and the bus controller also generate a three-clock cycle DMA transfer.
REFERENCES:
patent: 5111425 (1992-05-01), Takeuchi et al.
patent: 5297242 (1994-03-01), Miki
Coke James S.
Dahmani Dahmane
Dale Mitchell W.
Lent David D.
Rabe Jeffrey L.
Intel Corporation
Swann Tod R.
Thai Tuan V.
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