Method and apparatus for fast data transfer using internal clock

Details Method and apparatus for fast data transfer using internal clock Method and apparatus for fast data transfer using internal clock

1996-11-26

2000-06-27

Nguyen, Hiep T.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

710 52, 710 53, 710 60, 710 61, 713500, 713502, 713503, 713600, 711116, G06F 1202

Patent

active

060818778

ABSTRACT:
An apparatus for processing transfer data to be transferred in synchronism with one of an external write signal and an external read signal, includes a plurality of memories for storing the transfer data. A plurality of sync signal generators are provided in association with the memories, to generate one of a sync write signal and a sync read signal, which determine write and read timings for the memories, in response to one of the external write signal and the external read signal and an internal clock having a longer period than the one of said external write signal and the external read signal. A distribution circuit is connected to the plurality of sync signal generators, for receiving one of the external write signal and the external read signal and sequentially distributing the one of the external write signal and the external read signal to the sync signal generators. A plurality of address control circuits, are respectively connected between the memories and the sync signal generators, to control the memories in such a way as to write and read the transfer data into and from the memories in synchronism with one of the sync write signal and the sync read signal.

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