Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1996-10-17
2000-03-28
Le, Amanda T.
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
327148, 327157, 327163, 331 25, H03D 324
Patent
active
060441232
ABSTRACT:
A phase-locked loop with training capability that reduces the time for clock recovery of a clock signal at a known frequency embedded in a data signal. Prior to the data signal being available, the phase-locked loop, in a training mode, acquires frequency and phase lock with a local oscillator signal. As a result, the output of the PLL is frequency locked substantially at the frequency of the clock embedded in the expected data signal. To achieve this result, in the training mode, the PLL compares the local oscillator signal divided by a first divider with the output clock signal divided by a second divider. Then the frequency of the output clock signal of the PLL equals the frequency of the local oscillator multiplied by the ratio of the divisor of the second divider over the divisor of the first divider. When the data signal is available, the PLL operates in a data receiving mode. In that mode, the PLL typically only needs to acquire phase lock, since frequency lock already has been acquired in the training mode.
REFERENCES:
patent: 5258877 (1993-11-01), Leake et al.
patent: 5260979 (1993-11-01), Parker et al.
patent: 5276716 (1994-01-01), Wincn
patent: 5334952 (1994-08-01), Maddy et al.
patent: 5371425 (1994-12-01), Rogers
patent: 5386437 (1995-01-01), Yasuda
patent: 5487093 (1996-01-01), Adresen et al.
patent: 5525935 (1996-06-01), Joo et al.
patent: 5546433 (1996-08-01), Tran et al.
Chapter 3 entitled "The Classical Digital PLL (DPLl)" in book entitled Phase-Locked Loops; Theory, Design, and Applications by Roland E. Best published by McGraw-Hill, Inc., 1993.COPYRGT..
Hitachi Micro Systems Inc.
Le Amanda T.
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