Electrical computers and digital data processing systems: input/ – Interrupt processing – Programmable interrupt processing
Reexamination Certificate
2005-05-03
2005-05-03
Vo, Tim (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
Programmable interrupt processing
C710S266000, C710S267000, C710S261000
Reexamination Certificate
active
06889278
ABSTRACT:
A system and technique provides fast acknowledgement and servicing of interrupt sources coupled to a high latency path of an intermediate node of a computer network. An external device coupled to the high latency path is provided with a separate interrupt signal for each type of interrupt supported by a processor of the intermediate node. Each interrupt signal is directly fed to an interrupt multiplexing device over a first low latency path. The multiplexing device is accessible to the processor through a second low latency path. The external device asserts an interrupt by “pulsing” an appropriate interrupt signal to the multiplexing device. The multiplexing device maintains a current counter for each interrupt signal and increments that counter every time an interrupt pulse is detected. In addition to the counter, the multiplexing device maintains a status bit for each interrupt.
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Hoerler Johannes Markus
Sweet, Jr. Francis W.
Turner Joseph
Cesari and McKenna LLP
Cisco Technology Inc.
King Justin
Vo Tim
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