Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-04-05
2004-06-01
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06745372
ABSTRACT:
BACKGROUND
1. Field of the Invention
The invention relates to the process of designing an integrated circuit. More specifically, the invention relates to a method and an apparatus for simulating effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size.
2. Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. As the feature size of these circuit elements continues to decrease, circuit designers are forced to deal with problems that arise as a consequence of the optical lithography process that is typically used to manufacture the integrated circuits. This optical lithography process begins with the formation of a photoresist layer on the surface of a semiconductor wafer. A mask composed of opaque regions, which are formed of chrome, and light-transmissive clear regions, which are generally formed of quartz, is then positioned over this photoresist layer coated wafer. (Note that the term “mask” as used in this specification is meant to include the term “reticle.”) Light is then shone on the mask from a visible light source, an ultraviolet light source, or more generally some other type of electromagnetic radiation together with suitably adapted masks and lithography equipment.
This light is reduced and focused through an optical system that contains a number of lenses, filters and mirrors. The light passes through the clear regions of the mask and exposes the underlying photoresist layer. At the same time, the light is blocked by opaque regions of the mask, leaving underlying portions of the photoresist layer unexposed.
The exposed photoresist layer is then developed, through chemical removal of either the exposed or non-exposed regions of the photoresist layer. The end result is a semiconductor wafer with a photoresist layer having a desired pattern. This pattern can then be used for etching underlying regions of the wafer.
As feature sizes continue to decrease, optical effects, resist effects, mask writer beam effects, and/or other effects can degrade the quality of the printed image obtained through the optical lithography process. The upper portion of
FIG. 1
illustrates how an optical lithography process
102
converts a layout
510
into a printed image
113
on a semiconductor wafer. As mentioned above, this optical lithography process
102
involves: a mask fabrication process
104
, an exposure of the mask through stepper optics
106
, a photoresist development process
108
and a development or etching process
112
. Note that each of these processes can degrade the resulting printed image
113
.
A layout of an integrated circuit is typically created in accordance with a set of design rules that specify a number of constraints, such as minimum spacings or minimum line widths, to increase the likelihood that the finished integrated circuit functions properly in spite of different manufacturing effects. These design rules can be thought of as guidelines for a layout to circumvent process limitations.
It is advantageous to use such design rules because they simplify the layout process by hiding the complexity of the photolithography process. Design rules can be thought of as transforming a continuous problem into a discrete problem. Moreover, design rules can be easily verified by checking dimensions in the layout, such as minimum spacing between shapes.
However, the use of design rules can lead to sub-optimal layouts. For example, a design rule may specify a minimum spacing between specific shapes. However, a circuit designed using this minimum spacing may only function properly for a narrow range of variations in the manufacturing process. It may be preferable to use a larger spacing between shapes whenever possible to improve “process latitude”.
For this reason, some foundries have “recommended rules” to improve process latitude. The layout designer/tool uses these recommended rules in addition to standard design rules during the cell generation process to improve process latitude. The layout designer/tool attempts to satisfy these recommended rules. However, unlike standard design rules, they are not required to be satisfied. The layout designer/tool must relax minimum spacing, width and/or size between layout shapes to implement recommended rules. However, if recommended rules applied everywhere, they can lead to unnecessary expansion of the layout. The designer also has to make tradeoffs between recommended rules.
Hence, what is needed is a method and an apparatus for optimizing the spacing, width and/or size of layout shapes in order to enhance process latitude.
Note that in addition to the process latitude for standard design rules, there can be “fighter design rules” that decrease process latitude compared to standard design rules. There can also be “relaxed rules”, which increase process latitude compared to the standard design rules. Note that a recommended rule is a special case of a relaxed rule with a fixed value. Relaxed rules can allow for multiple values.
SUMMARY
One embodiment of the invention provides a system that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size. During operation, the system receives a representation of a target layout for the integrated circuit, wherein the representation defines a plurality of shapes that comprise the target layout. Next, the system simulates effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout. The system then identifies problem areas in the specification that do not meet a specification. Next, the system moves corresponding shapes in the target layout to produce a new target layout for the integrated circuit, so that a simulated printed image of the new target layout meets the specification.
Note that the above-described process differs from optical proximity correction. Optical proximity correction modifies a layout to compensate for optical effects so that the actual printed layout matches a target layout. In contrast, the above-described process moves shapes within the target layout to produce a new target layout that has better process latitude.
In a variation on this embodiment, moving the corresponding shapes in the target layout involves optimizing process latitude for the target layout.
In a variation on this embodiment, moving the corresponding shapes in the target layout involves performing a compaction process to minimize layout size.
In a variation on this embodiment; moving the corresponding shapes in the target layout involves providing objectives and/or constraints to the compaction process.
In a variation on this embodiment, moving the corresponding shapes in the target layout involves applying relaxed rules to the problem areas of the target layout to improve process latitude. In a further variation, the relaxed rules include priority values for resolving conflicts between relaxed rules.
In a variation on this embodiment, moving the corresponding shapes in the target layout involves applying relaxed rules to the problem areas of the target layout.
In a variation on this embodiment, the effects of the manufacturing process are simulated over a range of manufacturing parameters.
In a variation on this embodiment, the system additionally uses the simulated printed image to estimate a yield for the target layout.
In a variation on this embodiment, the system performs optical proximity correction (OPC) on the new target layout to produce a modified layout, wherein a simulated printed image of modified layout more closely matches the new target layout than the simulated printed image of the new target layout.
In a variation on this embodiment, the system uses information obtained from examining the simulated printed image to formulate new design rules for the target layout. These new design rules may be more aggressive tightened design rules. Alternatively, these new design rules can merely be diff
Côté Michel Luc
Hurat Philippe
Pierrat Christophe
Levin Naum B
Numerical Technologies Inc.
Park Vaughan & Fleming LLP
Siek Vuthe
LandOfFree
Method and apparatus for facilitating process-compliant... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for facilitating process-compliant..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for facilitating process-compliant... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3334793