Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral monitoring
Reexamination Certificate
1999-11-02
2002-08-13
Gaffin, Jeffrey (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral monitoring
C710S023000, C710S046000, C710S064000, C710S266000
Reexamination Certificate
active
06434633
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is in the field of computers and signal processing systems and circuits. More particularly, the invention is in the field of interfacing with peripherals through a codec.
2. Background Art
A codec (COder-DECoder) is a circuit that converts analog signals to digital code and vice versa using conversion methods such as PCM (Pulse Code Modulation). A codec typically includes both analog to digital and digital to analog conversion circuits.
FIG. 1
is a prior art diagram illustrating how a codec might be connected to a motherboard and in particular to a controller. Motherboard
110
is a modem PC motherboard. System logic
112
resides on motherboard
110
and is coupled to the remaining components on the motherboard primarily through a PCI (Peripheral Component Interconnect) bus
114
. A host CPU (not shown in any of the Figures) is typically located in system logic
112
. Controller
116
communicates with system logic
112
through PCI bus
114
. In
FIG. 1
, controller
116
is shown as a stand-alone device. However, controller
116
could be embedded or incorporated into other portions of the PC system including the system logic.
A riser
128
houses other components in FIG.
1
. Riser
128
complies with the industry's standard specification for an Audio/Modem Riser (or “AMR”). The AMR specification defines an industry standard form factor for Audio, Audio/Modem or just Modem risers. The AMR specification defines riser mechanical and electrical requirements for certain systems using what is called an AC-link (“Audio Codec link”) interface as one of the connections between the riser and the motherboard.
Referring to
FIG. 1
, riser
128
includes codec
126
. When riser
128
is plugged into motherboard
110
, codec
126
communicates with controller
116
through AC-link
124
, AMR interface connectors
122
and
120
, and AC-link
118
. Alternatively, the combination of AC-link
124
, AMR interface connectors
122
and
120
, and AC-link
118
can be thought of simply as a single AC-link connecting controller
116
to codec
126
.
Reference is made to
FIG. 2
which shows controller
216
that is coupled to codec
226
through AC-link
218
. Codec
226
includes codec register set
230
. Codec register set
230
is utilized by system and circuit design engineers for various control functions such as for configuring the codec or for setting up the codec to record a certain input such as a CD ROM input. As further examples, the registers in codec register set
230
are used for setting headphone volume, PC beep volume, microphone volume, CD volume, video volume, record gain,
3
D control, audio status, audio sample rate control, modem status, modem DAC/ADC level control, GPIO (General Purpose Input/Output) pin configuration, GPIO pin polarity and type, power management, as well as many other codec functions.
Typical codecs, such as those complying with the Intel® AC '97 specification entitled “AC '97 Component Specification,” Revision 2.1, published by Intel® Corporation on May 22, 1998 (or simply “AC '97 specification”), have been designed to perform primarily audio related functions. However, it has become increasingly important for codecs, such as those complying with AC '97 specification, to perform primarily modem related functions. Modem related functions can require additional modules and peripherals to be controlled by the controller. An example of when an additional module or peripheral and its respective set of registers need to be addressed and controlled through the AC-link is when it is desired to perform a DSP (“Digital Signal Processing”) function, such as acoustic echo cancellation, at a point beyond the AC-link and the codec (as opposed to performing the echo cancellation in the controller itself).
Other examples of additional modules or peripherals and their respective sets of registers that need to be addressed and controlled through the AC-link are an LSD (“Line Side Device”), an SSD (“System Side Device”), and an E-PHY (“Ethernet PHYsical-layer interface”) device. By way of background, an LSD is a module or peripheral that has been recently devised and added by some manufacturers to a Data Access Arrangement (“DAA”) device in order to facilitate the interfacing of the DAA with a codec. A DAA is a peripheral that is widely used in the art and is conventionally comprised of discrete components used to interface with a telephone line. As stated above, recently, the LSD has been added as a module in the DAA to facilitate interfacing between the DAA and a codec. With the recent addition of the LSD to the DAA by some manufacturers, the DAA is comprised of two main modules which are (a) the discrete component module, and (b) the LSD.
The addition of the LSD to the DAA has resulted in the need for addition of a module inside the codec to interface with the LSD. The module inside the codec is the SSD. The interface between the LSD which is outside the codec and the SSD which is inside the codec is performed through what is referred to as a Digital Isolation Barrier (“DIB”). The addition of the LSD and the SSD as recent modules that facilitate codec operations and which facilitate the codec interfacing with a telephone line, has given rise to the need to address and control these recently added modules, namely the LSD and the SSD, through the AC-link and the codec. It is noted that an SSD may also be a module separate from (as opposed to integrated in) the codec. An E-PHY is a device that performs Ethernet related functions in a LAN (“Local Area Network”). The E-PHY may be integrated in the codec or, alternatively, the E-PHY may be a module separate from the codec. Each of these modules or peripherals, e.g. the SSD, LSD, and E-PHY, has a respective set of registers which needs to be addressed and controlled by the controller through the AC-link.
As stated above, in each of the above examples the controller is required to address and control a bank of registers that are accessible to the controller only through the AC-link and the codec. In other words, in order to access modules or peripherals that are located “beyond” the AC-link, the controller must go through both the AC-link and the codec. As such, the controller must comply with the requirements of the AC-link. The requirements of the AC-link stem, in part, from a predetermined timing protocol for AC-link communications, i.e. for communications between the controller and the codec through the AC-link.
One specific requirement of an AC-link complying with the AC '97 specification has to do with timing and speed requirements for reading data by the controller from a register or a peripheral located across the AC-link. Transmission of data between controller
216
and codec
226
through AC-link
218
is performed in
12
outgoing or incoming “slots” following an initial “TAG” slot. According to the AC '97 specification, each “slot” contains up to twenty bits of information used for communication across AC-link
218
. The 12 slots following the TAG slot comprise a “frame.” The standard rate of transmission of frames through AC-link
218
, according to the AC '97 specification, is 48 KHz. In other words, in approximately every 20.8 microseconds, a frame is transmitted across AC-link
218
. This rate of transmission of frames across the AC-link is not adjustable for codecs complying with the AC '97 specification.
Moreover, the AC '97 specification imposes an exacting requirement that all read data be returned in the very next frame following the frame in which the read data was requested. In other words, when controller
216
makes a request to read a register located across AC-link
218
, the data from the addressed register must be returned to the controller in the very next frame, i.e. within approximately 20.8 microseconds from the read request.
This exacting standard poses a major problem when data to be read is not available because the register addressed is located in a slow periphe
Braun David P
Miller Mark E
Nuss Randy
Conexant Systems Inc.
Farjami & Farjami LLP
Mai Ri Jue
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