Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Reexamination Certificate
2005-03-30
2008-12-23
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Context preserving (e.g., context swapping, checkpointing,...
Reexamination Certificate
active
07469334
ABSTRACT:
One embodiment of the present invention provides a system that facilitates a fast execution restart following speculative execution. During normal operation of the system, a processor executes code on a non-speculative mode. Upon encountering a stall condition, the system checkpoints the state of the processor and executes the code in a speculative mode from the point of the stall. As the processor commences execution in speculative mode, it stores copies of instructions as they are issued into a recovery queue. When the stall condition is ultimately resolved, execution in non-speculative mode is recommenced and the execution units are initially loaded with instructions from the recovery queue, thereby avoiding the delay involved in waiting for instructions to propagate through the fetch and the decode stages of the pipeline. At the same time, the processor begins fetching subsequent instructions following the last instruction in the recovery queue. When all the instructions have been loaded from the recovery queue, the execution units begin receiving the subsequent instructions that have propagated through the fetch and decode stages of the pipeline.
REFERENCES:
patent: 5317701 (1994-05-01), Reininger et al.
patent: 5881280 (1999-03-01), Gupta et al.
patent: 6785803 (2004-08-01), Merchant et al.
patent: 6944718 (2005-09-01), Jouppi et al.
R. Barnes, E. Nystrom, J. Sias, S. Patel, N. Navarro, W. Hwu, Beating in-order stalls with “flea-flicker” two-pass pipelining, Dec. 2003, Proceedings of the 36th IEEE/ACM International Symposium on Micro-Architecture.
Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt, “Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors,” hpca, p. 129, The Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003.
Alvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson Koppanalil, Jaidev Patwardhan, “A Large, Fast Instruction Window for Tolerating Cache Misses,” isca, p. 0059, 29th Annual International Symposium on Computer Architecture (ISCA'02), 2002.
James Dundas and Trevor Mudge, “Improving Data Cache Performance by Pre-Executing Instructions Under a Cache Miss,” 11th ACM International Conference on Supercomputing, Jul. 1997.
Chaudhry Shailender
Jacobson Quinn A.
Tremblay Marc
Chan Eddie P
Park Vaughan & Fleming LLP
Petranek Jacob
Sun Microsystems Inc.
LandOfFree
Method and apparatus for facilitating a fast restart after... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for facilitating a fast restart after..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for facilitating a fast restart after... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4034333