Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2006-11-28
2006-11-28
Smith, Bradley K. (Department: 2891)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C257SE21575
Reexamination Certificate
active
07141511
ABSTRACT:
The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as DRAM or SRAM, various layers are deposited to form structures, such as PMOS gates, NMOS gates, memory cells, P+ active areas, and N+ active areas. These structures are fabricated through the use of multiple masking processes, which may cause shorts when a buried digit layer is deposited if the masking processes are misaligned. Accordingly, a dielectric etch stop layer, such as aluminum oxide Al2O3or silicon carbide SiC, may be utilized in the array to prevent shorts between the wordlines, active areas, and the buried digit layer when the contacts are misaligned.
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Fletcher Yoder PC
Micro)n Technology, Inc.
Smith Bradley K.
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