Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1995-10-13
1998-11-24
Ghebretinsae, Temesghen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
375360, 327160, H03D 324
Patent
active
058418237
ABSTRACT:
A clock signal is extracted from a received signal. An edge detector detects edges of the received signal, where the received signal transitions between a logic 0 and a logic 1. A center between each pair of consecutive edges is determined. Each center which is not within an associated correction window is discarded. An extracted clock signal is generated. The phase of the extracted clock signal is varied based on the centers between each pair of consecutive edges which are not discarded. In one embodiment, a current correction window size is varied based on whether an immediate previous center was within an immediate previous correction window. When the immediate previous center is discarded because it is not within the immediate previous correction window, the current correction window size is enlarged. When the immediate previous center is within the immediate previous correction window, and the immediate previous correction window is not already at a predetermined minimum size for correction windows, the current correction window size is reduced.
REFERENCES:
patent: 4847874 (1989-07-01), Kroeger et al.
patent: 4984255 (1991-01-01), Davis et al.
patent: 5519737 (1996-05-01), Brun et al.
patent: 5598446 (1997-01-01), Van Der Tuijn
European Telecommunication Standard (ETS) 300 175-2, European Telecommunications Standards Institute (ETSI), Reference DE/RES-3001-2, Oct. 1992, pp. 7,9,15,16,22 and 23.
European Telecommunication Standard (ETS) 300 175-3, European Telecommunications Standards Institute (ETSI), Reference DE/RES-3001-3, Oct. 1992, pp. 13,15,24,25,187,188.
Ghebretinsae Temesghen
VLSI Technology Inc.
Weller Douglas L.
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