Method and apparatus for extending the capabilities of tools...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10413081

ABSTRACT:
A method for designing a system on a PLD is disclosed according to a first embodiment of the present invention. A logic design is optimized. Logic circuits from the logic design are mapped to resources on the PLD. At least some of the resources are fitted onto locations on the PLD by utilizing a user-specified procedure.

REFERENCES:
patent: 6195788 (2001-02-01), Leaver et al.
patent: 6298319 (2001-10-01), Heile et al.
patent: 6321369 (2001-11-01), Heile et al.
patent: 6496972 (2002-12-01), Segal
patent: 6779169 (2004-08-01), Singh et al.
patent: 6823497 (2004-11-01), Schubert et al.
patent: 2004/0128641 (2004-07-01), Broberg et al.

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