Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-02-22
2002-09-03
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S612000, C438S613000, C257S737000, C257S779000, C228S180220
Reexamination Certificate
active
06444563
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor devices, and more particularly, to a method and apparatus for extending fatigue life of a semiconductor device.
BACKGROUND OF THE INVENTION
In the integrated circuit (IC) industry, ball grid array (BGA), chip scale packaging (CSP), and flip chip packaging technologies are beginning to gain wide acceptance and application. A general example of BGA or CSP technology is illustrated in
FIGS. 1-2
herein. Specifically,
FIG. 1
illustrates an integrated circuit die
10
that has bond pads
12
arranged in some two-dimensional layout across the IC's top surface. These bond pads
12
are exposed conductive regions that are coupled to underlying electrical components on the IC
10
. Through this coupling, the bond pads
12
allow the circuitry on the IC
10
to be electrically connected to other external devices, other peripherals, or other ICs over conductive traces of a printed circuit board (PCB) or other substrate whereby larger electrical systems may be created (e.g., a computer, a cell phone, a television, etc.). In the prior art
FIG. 1
, all bond pads
12
that electrically connect to circuitry on the die
10
are made the same size. This same or uniform bond pad size is usually set at a minimal size so that IC die area is optimally reduced thereby improving the profitability and performance of the IC. A uniform bond pad size also reduces manufacturing costs by simplifying the pad design and IC back-end processing.
FIG. 2
illustrates that only one conductive ball or conductive bump
14
is formed over each conductive bond pad
12
from FIG.
1
. In
FIG. 2
, each of the balls or bumps
14
are of a uniform size (i.e., a uniform volume of material is used to form each bump in FIG.
2
). Such uniform bump sizes are utilized in the industry to ensure a simple, low cost, high yield process while also ensuring that all bumps on the IC
10
are of the same standoff height. Standoff height is the distance a bump
14
rises above the top surface of the die
10
to which it is attached. It is desirable that all bumps
14
in
FIG. 2
rise a same vertical distance off the substrate
10
. If bumps
14
were to be formed having different heights over the die
10
, some tall bumps
14
may make electrical contact to a planar printed circuit board (PCB) while shorter bumps
14
may not make sufficient electrical contact to the PCB, whereby unacceptable electrical open circuits result. To ensure proper and uniform standoff height, the simple and uniform approach of forming a BGA or CSP design has been extensively used. In addition, by using this more simple uniform pad design, manufacturing costs are reduced whereby profit is maximized.
However, the bump technologies that use all uniformly sized bumps and uniformly sized bond pads have exhibited reduced field reliability primarily due to the smaller solder balls and smaller resultant solder joints between the IC substrate and the PCB. Smaller solder balls are required in most designs in order to meet the small size requirements for CSP devices, but the smaller sizes result in the formation of more fragile solder joint locations that can lead to a variety of field reliability failures. The overall IC device is only as good as its most fragile or most stressed solder joint. As a simple example, assume a BGA or CSP device has 5 solder joints or terminals, and that the reliability of these joints (a relibility value of 1 being the best and 9 being the worst) are 1, 2, 2, 4, and 9 respectively. In this design, the worst-case joint of 9 is the worst case joint. If one could improve the joint having a reliability value of 9 to a reliability value of 7, or any reliability value better than 9, the robustness of the example device would be greatly improved. If the reliability of the joint with the reliability value of 9 were increased to a reliability value of 2, then the new worst case joint would become the joint with the reliability value of 4. This is a substantial improvement over the previous design.
Therefore, a need exists in the industry for a method of selectively identifying and improving one or more worst case joints in an IC design whereby overall product reliability is greatly improved while the compactness of CSP and BGA devices is not substantially and adversely affected.
REFERENCES:
patent: 3871015 (1975-03-01), Lin et al.
patent: 5266520 (1993-11-01), Cipolla et al.
patent: 6020561 (2000-02-01), Ishida et al.
patent: 6066551 (2000-05-01), Satou
Katchmar et al., “Influencing Solder Joint Dependability in Area Array Packages,” The International Journal of Microcircuits and Electronic Packaging, vol. 20, No. 4, Fourth Quarter, pp. 545-555 (1997).
Satoh et al. “Development of a New Micro-Solder Bonding Method for VLSIs,” Proceedings of the Technical Conference, 3rd Annual International Electronics Packaging Conference, pp. 455-461 (1983).
Matsui et al., “VLSI Chip Interconnection Technology Using Stacked Solder Bumps,” Proceedings of 37th Electronic Components Conference, pp. 573-578 (1987).
Galloway Jesse E.
Gillette Joseph Guy
Johnson Zane Eric
Lall Pradeep
Potter Scott G.
Berezny Nema
Hill Daniel D.
Motorlla, Inc.
Nguyen Tuan H.
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