Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-05-26
2009-08-18
Abraham, Esaw T (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S786000, C714S799000
Reexamination Certificate
active
07577891
ABSTRACT:
A decoder architecture and method for implementing a decoder are provided. In one implementation, the decoder architecture includes an input buffer configured to receive a plurality of codewords to be processed, and includes an iterative decoder configured to receive a first codeword from the input buffer and process the first codeword. The iterative decoder processes the first codeword only for an amount of time required for the first codeword to become substantially error free. The decoder architecture further includes logic coupled to each of the iterative decoder and the input buffer. The logic is configured to determine when the first codeword processed by the decoder becomes substantially error free. The logic further generates a signal for loading a second codeword from the input buffer into the iterative decoder responsive to the logic determining when the first codeword becomes substantially error free.
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Farjad-rad Ramin
Shirani Ramin
Abraham Esaw T
Aquantia Corporation
Sawyer Law Group P.C.
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