Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-04-26
2005-04-26
Iqbal, Nadeem (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S742000
Reexamination Certificate
active
06886109
ABSTRACT:
A computer system includes multiple controllers that assist in executing the Power-On Self Test (POST) sequence to minimize the time required to complete system initialization. By shifting some of the responsibilities for executing the POST sequence to other controllers within the system, the testing and initialization of system devices can proceed concurrently. The controllers interface with peripheral devices, and include a register set that includes command information for initializing the testing and initialization of associated peripherals. The register set also includes dedicated bits for indicating the status of testing and initialization cycles, which can be read by the CPU to determine if testing or initialization is in progress, if it has completed, and if any errors have occurred. The register set also includes a configuration register for indicating configuration information and operating parameters of the initialized drive or peripheral. By distributing the testing and initialization responsibilities to the controllers, execution of the BIOS system software or system initialization software can be expedited, thus minimizing down time caused by initializing the computer system.
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Angelo Michael F.
Heng Chai S.
Olarig Sompong P.
Hewlett--Packard Development Company, L.P.
Iqbal Nadeem
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