Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-08-21
2007-08-21
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C430S005000
Reexamination Certificate
active
10910539
ABSTRACT:
One embodiment of the invention provides a system that expedites or stabilizes convergence in a model-based optical proximity correction (OPC) process. During operation, the system receives a layout for an integrated circuit. Next, the system dissects shapes in the layout into a number of segments, and then runs a number of OPC iterations on the segments to produce an OPC-corrected layout. During each OPC iteration, the system calculates a chrome shift for each segment based on a current layout obtained from the previous iteration, wherein the chrome shift for a segment is measured from the previous position of the chrome edge in that segment. The system then calculates an adjusted chrome shift for each segment based on the newly calculated chrome shift and chrome shift values obtained in one or more previous iterations. Next, the system applies the adjusted chrome shift values to the current layout to obtain an updated layout.
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Melvin, III Lawrence S.
Painter Benjamin
Chiang Jack
Park Vaughan & Fleming LLP
Rossoshek Helen
Synopsys, Inc
Yao Shun
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