Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1998-01-07
2000-10-03
Gossage, Glenn
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711146, 711167, 711119, 709248, G06F 1300
Patent
active
061287059
ABSTRACT:
A method and apparatus for preventing the occurrence of deadlocks from the execution of multiply-initiated multiply-sourced variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon condition. In other words, the snooper in a given cache can accept an operation and begin working on it even while retrying the operation. Furthermore, none of the active snoopers release an operation until all the active snoopers are done with the operation. In other words, execution of a given operation is started by the snoopers at the same time and finished by each of the snoopers at the same time. This prevents the ping-pong deadlock by keeping any one cache from finishing the operation before any of the others.
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Arimilli Ravi Kumar
Kaiser, deceased John Michael
Williams Derek Edward
Gossage Glenn
Henkler Richard A.
International Business Machines - Corporation
McBurney Mark E.
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