Electrical computers and digital processing systems: support – Computer power control – Power sequencing
Reexamination Certificate
2000-12-26
2004-08-17
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Computer power control
Power sequencing
C713S322000, C712S205000
Reexamination Certificate
active
06779122
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains generally to computers. In particular, it pertains to reducing current surges during the operation of microprocessors.
2. Description of the Related Art
Many motherboard designs use voltage regulators to supply the power requirements of high performance processors (CPUs). These voltage regulators attempt to keep a constant voltage level as the current requirements of the CPU change. However, voltage regulators have a minimum response time, so if the current demand increases too quickly, the CPU may experience a temporary drop in its supply voltage until the voltage regulator can respond to this increased current demand. The rate of change in current is commonly expressed as di/dt, indicating the amount of change in current divided by amount of time during which the change occurs.
Unfortunately, the current requirements of conventional processors can vary suddenly and considerably during operation as the processors go into and out of various power saving modes. At least one power saving mode, commonly referred to as a sleep mode, stops the clock that controls the processor circuitry. Since processor clocks can operate at a speed of hundreds of megahertz, it may require only a very small fraction of a microsecond for a processor enter or exit a sleep mode, and the processor's electrical current requirement can change just as rapidly.
A conventional processor enters a sleep mode after the processor receives a signal requesting it to stop its clock. This stop-clock signal can be generated by an external power management circuit and received on an input pin of the processor. Alternately, it might be generated internally when the CPU executes a HALT instruction. There are typically processes in work in the CPU that should be completed before entering a sleep mode, so when the stop-clock signal is received, the processor will go through a sequence in its micro-code that performs several functions. These functions typically include:
1) Stop the instruction fetch unit from fetching instructions.
2) Wait for the cache buffers to finish writing data into cache, so that no cache data will be lost.
3) Wait for the processor bus output queue to finish writing data onto the processor bus, so that all pending writes from the CPU can reach their destination.
4) Write to a control register to turn the processor clock off.
At this point, the processor clock (or clocks, if more than one processor clock is being used) stops, which freezes all internal operations in the CPU. When an event occurs to bring the processor out of sleep mode, the clock will be restarted. This might occur by removing the stop-clock signal from the CPUs input pin, or it could be triggered by an interrupt. In either case, when the clock is restarted, the CPU continues execution of the instruction that was being executed when the clock stopped. After execution of that instruction is completed, the micro-code sequence performs another step by restarting the instruction fetch unit. This permits execution of program instructions to return to normal.
When the clock is restarted, it may only take one clock cycle for the current instruction to complete its execution and the instruction fetch unit to be turned on. This effectively causes all circuitry involved in instruction execution to begin operating at the same time, and the cumulative current requirements of all this circuitry place a substantially increased current demand on the system within one clock cycle. The voltage regulator cannot keep up with this high di/dt requirement, and a drop in voltage may be experienced by the CPU. If this drop is large enough, it can cause errors in CPU operation.
Conventional designs attempt to minimize this problem by placing bulk decoupling capacitors between the output of the voltage regulator and the voltage inputs of the CPU. The charge stored in these capacitors can supply some of the current needed until the voltage regulator can respond. However, this approach has several drawbacks. Capacitors are expensive, and require a lot of space that could be used for other circuit needs. Also, capacitors on the motherboard may be too far away from the current-consuming portions of the CPU chip to supply the needed current quickly enough. Although capacitors can be designed into the chip itself, these also require space that could be better used for other circuitry.
REFERENCES:
patent: 5414863 (1995-05-01), Lee et al.
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patent: 6100752 (2000-08-01), Lee et al.
patent: 6128747 (2000-10-01), Thoulon
patent: 11306016 (1999-11-01), None
patent: 2000222279 (2000-08-01), None
Larsson Mikael, Re: Variably clocked processors?, Aug. 5, 1994.
Chan Tim W.
George Varghese
Connolly Mark
Lee Thomas
Travis John F.
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