Patent
1996-03-19
1997-12-02
Harvey, Jack B.
395285, 395309, G06F 1300
Patent
active
056945558
ABSTRACT:
Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.
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Bhatt Ajay V.
Cadambi Sudarshan Bala
Haslam Richard M.
Knoll Shaun
Morriss Jeff Charles
Harvey Jack B.
Intel Corporation
Travis John
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