Method and apparatus for event simulation

Electrical computers and digital processing systems: support – Multiple computer communication using cryptography – Protection at a particular protocol layer

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

39550037, 395874, 713502, G06F 9455

Patent

active

060060271

ABSTRACT:
A method and apparatus for inserting an event into a simulation time queue, wherein the simulation time queue is represented by a tree structure having a top node which represents the total number of "time slices" to be simulated, intermediate nodes representing subsets of time slices within the total number of time slices to be simulated, and event locations representing events to be simulated. A time slice is defined to represent a minimum resolvable time period within the simulation. The method includes the steps of choosing a starting node within the tree structure, designating it as the current location, determining whether the current location is an intermediate node representing a range of time slices of which the time slice of the event to be inserted is a subset, determining, if the current location is such an intermediate node, if any existing child nodes of said current location are event locations, and if so, adding the event to the proper event location of said current location.

REFERENCES:
patent: 4796178 (1989-01-01), Jennings et al.
patent: 4914569 (1990-04-01), Levine et al.
patent: 5197002 (1993-03-01), Spencer
patent: 5202986 (1993-04-01), Nickel
patent: 5204958 (1993-04-01), Cheng et al.
patent: 5283894 (1994-02-01), Deran
patent: 5418947 (1995-05-01), Hsu et al.
patent: 5423018 (1995-06-01), Dang et al.
patent: 5463562 (1995-10-01), Theobald
patent: 5465335 (1995-11-01), Anderson
patent: 5467462 (1995-11-01), Fujii
patent: 5497485 (1996-03-01), Ferguson et al.
patent: 5519701 (1996-05-01), Colmant et al.
patent: 5544348 (1996-08-01), Umeda et al.
patent: 5560007 (1996-09-01), Thai
patent: 5581756 (1996-12-01), Nakabayashi
patent: 5684724 (1997-11-01), Sutherland
patent: 5764953 (1998-06-01), Collins et al.
patent: 5856933 (1999-01-01), Maurer
P. Gillard et al., "A Hierarchical View of Time", Proceedings of the 34th Midwest Symposium on Circuits and Systems, IEEE, 1992, pp. 908-911, vol. 2.
G. Beihl, "A Shared-Memory Multiprocessor Logic Simulator", 8th Annual Int'l Phoenix Conf. Proceedings on Computers and Communications, IEEE, 1989, pp. 26-28.
B. Ackland et al., "Event-EMU: An Event Driven Timing Simulator for MOS VLSI Circuits", 1989 IEEE Int'l Conf. on Computer-Aided Design, ICCAD-89, Digest of Technical Papers, pp. 80-83.
A. Brown et al., "Issues in the Design of a Logic Simulator: An Improved Caching Technique for Event-Queue Management", IEE Proceedings--Circuits, Devices and Systems, Oct. 1995, vol. 142 5, pp. 293-298.
S. Prasad et al., "Using Parallel Data Structures in Optimistic Discrete Eevent Simulation of Varying Ganularity on Shared-Memory Computers", IEEE !st Int'l Conf. On Algorithms and Architectures for Parallel Processing, 1995, ICAPP 95, pp. 365-374, vol. 1.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for event simulation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for event simulation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for event simulation will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-514113

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.